From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 15 Jun 2018 20:44:06 +0300 Subject: drm/i915: Enforce max hdisplay/hblank_start limits on HSW/BDW FDI MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Git-commit: ad193bc6206d3ee2fc39fe29a2525333faf1afd9 Patch-mainline: v4.19-rc1 References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166 The PCH transcoder registers are only 12 bits wide for the hdisplay and hblank_start values. On HSW/BDW the CPU side registers are 13 bits wide. intel_mode_valid() only checks against the higher limit (since we don't know where the mode is to be used), so an extra check is required against the FDI limits. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20180615174406.12258-3-ville.syrjala@linux.intel.com Reviewed-by: Paulo Zanoni Acked-by: Petr Tesarik --- drivers/gpu/drm/i915/intel_crt.c | 9 +++++++++ 1 file changed, 9 insertions(+) --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c @@ -337,6 +337,10 @@ intel_crt_mode_valid(struct drm_connecto (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) return MODE_CLOCK_HIGH; + /* HSW/BDW FDI limited to 4k */ + if (mode->hdisplay > 4096) + return MODE_H_ILLEGAL; + return MODE_OK; } @@ -379,6 +383,11 @@ static bool hsw_crt_compute_config(struc if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) return false; + /* HSW/BDW FDI limited to 4k */ + if (adjusted_mode->crtc_hdisplay > 4096 || + adjusted_mode->crtc_hblank_start > 4096) + return false; + pipe_config->has_pch_encoder = true; /* LPT FDI RX only supports 8bpc. */