From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Wed, 21 Feb 2018 18:02:30 +0200 Subject: drm/i915: Fail if we can't get a fence for gen2/3 tiled scanout MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Git-commit: 85798ac9b35f8cc7608a4a798d0b0626f0d54d61 Patch-mainline: v4.17-rc1 References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166 Gen2/3 display engine depends on the fence for tiled scanout. So if we fail to get a fence fail the entire operation. Cc: Chris Wilson Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20180221160235.11134-2-ville.syrjala@linux.intel.com Reviewed-by: Chris Wilson Acked-by: Petr Tesarik --- drivers/gpu/drm/i915/intel_display.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2123,6 +2123,8 @@ intel_pin_and_fence_fb_obj(struct drm_fr goto err; if (i915_vma_is_map_and_fenceable(vma)) { + int ret; + /* Install a fence for tiled scan-out. Pre-i965 always needs a * fence, whereas 965+ only requires a fence if using * framebuffer compression. For simplicity, we always, when @@ -2139,7 +2141,13 @@ intel_pin_and_fence_fb_obj(struct drm_fr * something and try to run the system in a "less than optimal" * mode that matches the user configuration. */ - if (i915_vma_pin_fence(vma) == 0 && vma->fence) + ret = i915_vma_pin_fence(vma); + if (ret != 0 && INTEL_GEN(dev_priv) < 4) { + vma = ERR_PTR(ret); + goto err; + } + + if (ret == 0 && vma->fence) *out_flags |= PLANE_HAS_FENCE; }