From: Nikola Cornij Date: Fri, 27 Apr 2018 17:26:25 -0400 Subject: drm/amd/display: Clear underflow status for debug purposes Git-commit: a944744ba517256fcc9311e12c083563cbbe7c88 Patch-mainline: v4.18-rc1 References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166 We want to keep underflow sticky bit on for the longevity tests outside of test environment. For debug purposes it is, however, useful to clear underflow status after the test that caused it so that the following tests are not affected. This change fullfils both requirements by clearing the underflow only from within Windows or Diags test environment. Signed-off-by: Nikola Cornij Reviewed-by: Nikola Cornij Acked-by: Harry Wentland Signed-off-by: Alex Deucher Acked-by: Petr Tesarik --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 6 ++++++ 1 file changed, 6 insertions(+) --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -326,6 +326,12 @@ void dcn10_log_hw_state(struct dc *dc) s.h_total, s.v_total, s.underflow_occurred_status); + + // Clear underflow for debug purposes + // We want to keep underflow sticky bit on for the longevity tests outside of test environment. + // This function is called only from Windows or Diags test environment, hence it's safe to clear + // it from here without affecting the original intent. + tg->funcs->clear_optc_underflow(tg); } DTN_INFO("\n");