diff --git a/patches.suse/Revert-Revert-drm-amdgpu-display-change-pipe-policy-.patch b/patches.suse/Revert-Revert-drm-amdgpu-display-change-pipe-policy-.patch new file mode 100644 index 0000000..bb82236 --- /dev/null +++ b/patches.suse/Revert-Revert-drm-amdgpu-display-change-pipe-policy-.patch @@ -0,0 +1,42 @@ +From 6ecc10295abb2fdd9c21dd17b34e4cacfd829cd4 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Tue, 15 Aug 2023 17:25:37 -0400 +Subject: [PATCH] Revert "Revert "drm/amdgpu/display: change pipe policy for DCN 2.0"" +Git-commit: 6ecc10295abb2fdd9c21dd17b34e4cacfd829cd4 +Alt-commit: ef35c7ba60410926d0501e45aad299656a83826c +Patch-mainline: v6.5-rc7 +References: git-fixes + +This reverts commit 27dd79c00aeab36cd7542c7a4481a32549038659. + +It appears MPC_SPLIT_DYNAMIC still causes problems with multiple +displays on DCN2.0 hardware. Switch back to MPC_SPLIT_AVOID_MULT_DISP. +This increases power usage with multiple displays, but avoids hangs. + +Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2475 +Cc: Rodrigo Siqueira +Reviewed-by: Harry Wentland +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org # 6.4.x +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +index 4cc8de2627ce..9f2e24398cd7 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +@@ -712,7 +712,7 @@ static const struct dc_debug_options debug_defaults_drv = { + .timing_trace = false, + .clock_trace = true, + .disable_pplib_clock_request = true, +- .pipe_split_policy = MPC_SPLIT_DYNAMIC, ++ .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, + .force_single_disp_pipe_split = false, + .disable_dcc = DCC_ENABLE, + .vsr_support = true, +-- +2.43.0 + diff --git a/patches.suse/Revert-drm-amd-Disable-PSR-SU-on-Parade-0803-TCON.patch b/patches.suse/Revert-drm-amd-Disable-PSR-SU-on-Parade-0803-TCON.patch new file mode 100644 index 0000000..84f576e --- /dev/null +++ b/patches.suse/Revert-drm-amd-Disable-PSR-SU-on-Parade-0803-TCON.patch @@ -0,0 +1,41 @@ +From 1e66a17ce546eabad753178bbd4175cb52bafca8 Mon Sep 17 00:00:00 2001 +From: Mario Limonciello +Date: Fri, 23 Jun 2023 10:05:22 -0500 +Subject: [PATCH] Revert "drm/amd: Disable PSR-SU on Parade 0803 TCON" +Git-commit: 1e66a17ce546eabad753178bbd4175cb52bafca8 +Patch-mainline: v6.5-rc1 +References: git-fixes + +This reverts commit 072030b1783056b5de8b0fac5303a5e9dbc6cfde. +This is no longer necessary when using newer DMUB F/W. + +Cc: stable@vger.kernel.org +Cc: Sean Wang +Cc: Marc Rossi +Cc: Hamza Mahfooz +Cc: Tsung-hua (Ryan) Lin +Reviewed-by: Leo Li +Signed-off-by: Mario Limonciello +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/modules/power/power_helpers.c | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c +index b9e78451a3d5..30349881a283 100644 +--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c ++++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c +@@ -839,8 +839,6 @@ bool is_psr_su_specific_panel(struct dc_link *link) + ((dpcd_caps->sink_dev_id_str[1] == 0x08 && dpcd_caps->sink_dev_id_str[0] == 0x08) || + (dpcd_caps->sink_dev_id_str[1] == 0x08 && dpcd_caps->sink_dev_id_str[0] == 0x07))) + isPSRSUSupported = false; +- else if (dpcd_caps->sink_dev_id_str[1] == 0x08 && dpcd_caps->sink_dev_id_str[0] == 0x03) +- isPSRSUSupported = false; + else if (dpcd_caps->psr_info.force_psrsu_cap == 0x1) + isPSRSUSupported = true; + } +-- +2.43.0 + diff --git a/patches.suse/Revert-drm-amd-Disable-S-G-for-APUs-when-64GB-or-mor.patch b/patches.suse/Revert-drm-amd-Disable-S-G-for-APUs-when-64GB-or-mor.patch new file mode 100644 index 0000000..35a156a --- /dev/null +++ b/patches.suse/Revert-drm-amd-Disable-S-G-for-APUs-when-64GB-or-mor.patch @@ -0,0 +1,95 @@ +From 169ed4ece8373f02f10642eae5240e3d1ef5c038 Mon Sep 17 00:00:00 2001 +From: Hamza Mahfooz +Date: Fri, 8 Sep 2023 10:36:44 -0400 +Subject: [PATCH] Revert "drm/amd: Disable S/G for APUs when 64GB or more host memory" +Git-commit: 169ed4ece8373f02f10642eae5240e3d1ef5c038 +Patch-mainline: v6.6-rc2 +References: git-fixes + +This reverts commit 70e64c4d522b732e31c6475a3be2349de337d321. + +Since, we now have an actual fix for this issue, we can get rid of this +workaround as it can cause pin failures if enough VRAM isn't carved out +by the BIOS. + +Cc: stable@vger.kernel.org # 6.1+ +Acked-by: Harry Wentland +Reviewed-by: Alex Deucher +Signed-off-by: Hamza Mahfooz +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 - + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 26 ------------------- + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 ++-- + 3 files changed, 3 insertions(+), 29 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +index dc2d53081e80..a79d53bdbe13 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +@@ -1293,7 +1293,6 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, + void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); + int amdgpu_device_pci_reset(struct amdgpu_device *adev); + bool amdgpu_device_need_post(struct amdgpu_device *adev); +-bool amdgpu_sg_display_supported(struct amdgpu_device *adev); + bool amdgpu_device_pcie_dynamic_switching_supported(void); + bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); + bool amdgpu_device_aspm_support_quirk(void); +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +index 3f001a50b34a..30c4f5cca02c 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +@@ -1244,32 +1244,6 @@ bool amdgpu_device_need_post(struct amdgpu_device *adev) + return true; + } + +-/* +- * On APUs with >= 64GB white flickering has been observed w/ SG enabled. +- * Disable S/G on such systems until we have a proper fix. +- * https://gitlab.freedesktop.org/drm/amd/-/issues/2354 +- * https://gitlab.freedesktop.org/drm/amd/-/issues/2735 +- */ +-bool amdgpu_sg_display_supported(struct amdgpu_device *adev) +-{ +- switch (amdgpu_sg_display) { +- case -1: +- break; +- case 0: +- return false; +- case 1: +- return true; +- default: +- return false; +- } +- if ((totalram_pages() << (PAGE_SHIFT - 10)) + +- (adev->gmc.real_vram_size / 1024) >= 64000000) { +- DRM_WARN("Disabling S/G due to >=64GB RAM\n"); +- return false; +- } +- return true; +-} +- + /* + * Intel hosts such as Raptor Lake and Sapphire Rapids don't support dynamic + * speed switching. Until we have confirmation from Intel that a specific host +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +index 6a0ea15936ae..954906c515aa 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -1644,8 +1644,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) + } + break; + } +- if (init_data.flags.gpu_vm_support) +- init_data.flags.gpu_vm_support = amdgpu_sg_display_supported(adev); ++ if (init_data.flags.gpu_vm_support && ++ (amdgpu_sg_display == 0)) ++ init_data.flags.gpu_vm_support = false; + + if (init_data.flags.gpu_vm_support) + adev->mode_info.gpu_vm_support = true; +-- +2.43.0 + diff --git a/patches.suse/Revert-drm-amdgpu-display-change-pipe-policy-for-DCN-27dd79c.patch b/patches.suse/Revert-drm-amdgpu-display-change-pipe-policy-for-DCN-27dd79c.patch new file mode 100644 index 0000000..9685a8b --- /dev/null +++ b/patches.suse/Revert-drm-amdgpu-display-change-pipe-policy-for-DCN-27dd79c.patch @@ -0,0 +1,40 @@ +From 27dd79c00aeab36cd7542c7a4481a32549038659 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Tue, 28 Feb 2023 14:46:46 -0500 +Subject: [PATCH] Revert "drm/amdgpu/display: change pipe policy for DCN 2.0" +Git-commit: 27dd79c00aeab36cd7542c7a4481a32549038659 +Patch-mainline: v6.4-rc1 +References: git-fixes + +This reverts commit bcfab8e35ce81e2fd3230c1575024bfde0d28c8b. + +Hopefully this is fixed by the previous patch to enable +TEMP_DEPENDENT_VMIN for navi1x or otherwise and we can re-enable +MPC_SPLIT_DYNAMIC for DCN 2.0 for better power savings. + +Reviewed-by: Rodrigo Siqueira +Acked-by: Qingqing Zhuo +Signed-off-by: Alex Deucher +Tested-by: Daniel Wheeler +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +index 77ef474ced07..1d8c5805ef20 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +@@ -712,7 +712,7 @@ static const struct dc_debug_options debug_defaults_drv = { + .timing_trace = false, + .clock_trace = true, + .disable_pplib_clock_request = true, +- .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, ++ .pipe_split_policy = MPC_SPLIT_DYNAMIC, + .force_single_disp_pipe_split = false, + .disable_dcc = DCC_ENABLE, + .vsr_support = true, +-- +2.43.0 + diff --git a/patches.suse/Revert-drm-amdgpu-display-change-pipe-policy-for-DCN.patch b/patches.suse/Revert-drm-amdgpu-display-change-pipe-policy-for-DCN.patch new file mode 100644 index 0000000..c292359 --- /dev/null +++ b/patches.suse/Revert-drm-amdgpu-display-change-pipe-policy-for-DCN.patch @@ -0,0 +1,39 @@ +From 83923cb27323139f9e2185db9b3b1299e6cf22bc Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Tue, 28 Feb 2023 14:54:43 -0500 +Subject: [PATCH] Revert "drm/amdgpu/display: change pipe policy for DCN 2.1" +Git-commit: 83923cb27323139f9e2185db9b3b1299e6cf22bc +Patch-mainline: v6.4-rc1 +References: git-fixes + +This reverts commit fa458eb10dc7218146a84e6d2e072424e64d188a. + +The issue is no longer present even with this commit present +as verified by the original reporter. + +Reviewed-by: Rodrigo Siqueira +Signed-off-by: Alex Deucher +Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1849#note_1759599 +Signed-off-by: Rodrigo Siqueira +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +index 8f9244fe5c86..c10ff621cb1d 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +@@ -642,7 +642,7 @@ static const struct dc_debug_options debug_defaults_drv = { + .clock_trace = true, + .disable_pplib_clock_request = true, + .min_disp_clk_khz = 100000, +- .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, ++ .pipe_split_policy = MPC_SPLIT_DYNAMIC, + .force_single_disp_pipe_split = false, + .disable_dcc = DCC_ENABLE, + .vsr_support = true, +-- +2.43.0 + diff --git a/patches.suse/Revert-drm-vc4-hdmi-Enforce-the-minimum-rate-at-runt.patch b/patches.suse/Revert-drm-vc4-hdmi-Enforce-the-minimum-rate-at-runt.patch new file mode 100644 index 0000000..0c4fc92 --- /dev/null +++ b/patches.suse/Revert-drm-vc4-hdmi-Enforce-the-minimum-rate-at-runt.patch @@ -0,0 +1,44 @@ +From 9a87e28da1f3563977bef1b6754e3d5d6895546f Mon Sep 17 00:00:00 2001 +From: Maxime Ripard +Date: Thu, 26 Jan 2023 18:05:49 +0100 +Subject: [PATCH] Revert "drm/vc4: hdmi: Enforce the minimum rate at runtime_resume" +Git-commit: 9a87e28da1f3563977bef1b6754e3d5d6895546f +Patch-mainline: v6.4-rc1 +References: git-fixes + +This reverts commit ae71ab585c819f83aec84f91eb01157a90552ef2. + +Commit ae71ab585c81 ("drm/vc4: hdmi: Enforce the minimum rate at +runtime_resume") was introduced to work around an issue partly due to +the clk-bcm2835 driver on the RaspberryPi0-3. + +Since we're not using that driver for our HDMI clocks, we can now revert +it. + +Reviewed-by: Javier Martinez Canillas +Link: https://lore.kernel.org/r/20230126-rpi-display-fw-clk-cleanup-v1-4-d646ff6fb842@cerno.tech +Signed-off-by: Maxime Ripard +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/vc4/vc4_hdmi.c | 9 --------- + 1 file changed, 9 deletions(-) + +--- a/drivers/gpu/drm/vc4/vc4_hdmi.c ++++ b/drivers/gpu/drm/vc4/vc4_hdmi.c +@@ -2872,15 +2872,6 @@ static int vc4_hdmi_runtime_resume(struc + u32 __maybe_unused value; + int ret; + +- /* +- * The HSM clock is in the HDMI power domain, so we need to set +- * its frequency while the power domain is active so that it +- * keeps its rate. +- */ +- ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ); +- if (ret) +- return ret; +- + ret = clk_prepare_enable(vc4_hdmi->hsm_clock); + if (ret) + return ret; diff --git a/patches.suse/crypto-arm-sha-fix-function-cast-warnings.patch b/patches.suse/crypto-arm-sha-fix-function-cast-warnings.patch new file mode 100644 index 0000000..2c30bf1 --- /dev/null +++ b/patches.suse/crypto-arm-sha-fix-function-cast-warnings.patch @@ -0,0 +1,115 @@ +From 53cc9baeb9bc2a187eb9c9790d30995148852b12 Mon Sep 17 00:00:00 2001 +From: Arnd Bergmann +Date: Tue, 13 Feb 2024 14:49:46 +0100 +Subject: [PATCH] crypto: arm/sha - fix function cast warnings +Git-commit: 53cc9baeb9bc2a187eb9c9790d30995148852b12 +Patch-mainline: v6.9-rc1 +References: git-fixes + +clang-16 warns about casting between incompatible function types: + +arch/arm/crypto/sha256_glue.c:37:5: error: cast from 'void (*)(u32 *, const void *, unsigned int)' (aka 'void (*)(unsigned int *, const void *, unsigned int)') to 'sha256_block_fn *' (aka 'void (*)(struct sha256_state *, const unsigned char *, int)') converts to incompatible function type [-Werror,-Wcast-function-type-strict] + 37 | (sha256_block_fn *)sha256_block_data_order); + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +arch/arm/crypto/sha512-glue.c:34:3: error: cast from 'void (*)(u64 *, const u8 *, int)' (aka 'void (*)(unsigned long long *, const unsigned char *, int)') to 'sha512_block_fn *' (aka 'void (*)(struct sha512_state *, const unsigned char *, int)') converts to incompatible function type [-Werror,-Wcast-function-type-strict] + 34 | (sha512_block_fn *)sha512_block_data_order); + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Fix the prototypes for the assembler functions to match the typedef. +The code already relies on the digest being the first part of the +state structure, so there is no change in behavior. + +Fixes: c80ae7ca3726 ("crypto: arm/sha512 - accelerated SHA-512 using ARM generic ASM and NEON") +Fixes: b59e2ae3690c ("crypto: arm/sha256 - move SHA-224/256 ASM/NEON implementation to base layer") +Signed-off-by: Arnd Bergmann +Reviewed-by: Ard Biesheuvel +Signed-off-by: Herbert Xu +Acked-by: Takashi Iwai + +--- + arch/arm/crypto/sha256_glue.c | 13 +++++-------- + arch/arm/crypto/sha512-glue.c | 12 +++++------- + 2 files changed, 10 insertions(+), 15 deletions(-) + +diff --git a/arch/arm/crypto/sha256_glue.c b/arch/arm/crypto/sha256_glue.c +index 433ee4ddce6c..f85933fdec75 100644 +--- a/arch/arm/crypto/sha256_glue.c ++++ b/arch/arm/crypto/sha256_glue.c +@@ -24,8 +24,8 @@ + + #include "sha256_glue.h" + +-asmlinkage void sha256_block_data_order(u32 *digest, const void *data, +- unsigned int num_blks); ++asmlinkage void sha256_block_data_order(struct sha256_state *state, ++ const u8 *data, int num_blks); + + int crypto_sha256_arm_update(struct shash_desc *desc, const u8 *data, + unsigned int len) +@@ -33,23 +33,20 @@ int crypto_sha256_arm_update(struct shash_desc *desc, const u8 *data, + /* make sure casting to sha256_block_fn() is safe */ + BUILD_BUG_ON(offsetof(struct sha256_state, state) != 0); + +- return sha256_base_do_update(desc, data, len, +- (sha256_block_fn *)sha256_block_data_order); ++ return sha256_base_do_update(desc, data, len, sha256_block_data_order); + } + EXPORT_SYMBOL(crypto_sha256_arm_update); + + static int crypto_sha256_arm_final(struct shash_desc *desc, u8 *out) + { +- sha256_base_do_finalize(desc, +- (sha256_block_fn *)sha256_block_data_order); ++ sha256_base_do_finalize(desc, sha256_block_data_order); + return sha256_base_finish(desc, out); + } + + int crypto_sha256_arm_finup(struct shash_desc *desc, const u8 *data, + unsigned int len, u8 *out) + { +- sha256_base_do_update(desc, data, len, +- (sha256_block_fn *)sha256_block_data_order); ++ sha256_base_do_update(desc, data, len, sha256_block_data_order); + return crypto_sha256_arm_final(desc, out); + } + EXPORT_SYMBOL(crypto_sha256_arm_finup); +diff --git a/arch/arm/crypto/sha512-glue.c b/arch/arm/crypto/sha512-glue.c +index 0635a65aa488..1be5bd498af3 100644 +--- a/arch/arm/crypto/sha512-glue.c ++++ b/arch/arm/crypto/sha512-glue.c +@@ -25,27 +25,25 @@ MODULE_ALIAS_CRYPTO("sha512"); + MODULE_ALIAS_CRYPTO("sha384-arm"); + MODULE_ALIAS_CRYPTO("sha512-arm"); + +-asmlinkage void sha512_block_data_order(u64 *state, u8 const *src, int blocks); ++asmlinkage void sha512_block_data_order(struct sha512_state *state, ++ u8 const *src, int blocks); + + int sha512_arm_update(struct shash_desc *desc, const u8 *data, + unsigned int len) + { +- return sha512_base_do_update(desc, data, len, +- (sha512_block_fn *)sha512_block_data_order); ++ return sha512_base_do_update(desc, data, len, sha512_block_data_order); + } + + static int sha512_arm_final(struct shash_desc *desc, u8 *out) + { +- sha512_base_do_finalize(desc, +- (sha512_block_fn *)sha512_block_data_order); ++ sha512_base_do_finalize(desc, sha512_block_data_order); + return sha512_base_finish(desc, out); + } + + int sha512_arm_finup(struct shash_desc *desc, const u8 *data, + unsigned int len, u8 *out) + { +- sha512_base_do_update(desc, data, len, +- (sha512_block_fn *)sha512_block_data_order); ++ sha512_base_do_update(desc, data, len, sha512_block_data_order); + return sha512_arm_final(desc, out); + } + +-- +2.43.0 + diff --git a/patches.suse/crypto-xilinx-call-finalize-with-bh-disabled.patch b/patches.suse/crypto-xilinx-call-finalize-with-bh-disabled.patch new file mode 100644 index 0000000..244db5e --- /dev/null +++ b/patches.suse/crypto-xilinx-call-finalize-with-bh-disabled.patch @@ -0,0 +1,72 @@ +From a853450bf4c752e664abab0b2fad395b7ad7701c Mon Sep 17 00:00:00 2001 +From: Quanyang Wang +Date: Sun, 28 Jan 2024 12:29:06 +0800 +Subject: [PATCH] crypto: xilinx - call finalize with bh disabled +Git-commit: a853450bf4c752e664abab0b2fad395b7ad7701c +Patch-mainline: v6.9-rc1 +References: git-fixes + +When calling crypto_finalize_request, BH should be disabled to avoid +triggering the following calltrace: + + ------------[ cut here ]------------ + WARNING: CPU: 2 PID: 74 at crypto/crypto_engine.c:58 crypto_finalize_request+0xa0/0x118 + Modules linked in: cryptodev(O) + CPU: 2 PID: 74 Comm: firmware:zynqmp Tainted: G O 6.8.0-rc1-yocto-standard #323 + Hardware name: ZynqMP ZCU102 Rev1.0 (DT) + pstate: 40000005 (nZcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) + pc : crypto_finalize_request+0xa0/0x118 + lr : crypto_finalize_request+0x104/0x118 + sp : ffffffc085353ce0 + x29: ffffffc085353ce0 x28: 0000000000000000 x27: ffffff8808ea8688 + x26: ffffffc081715038 x25: 0000000000000000 x24: ffffff880100db00 + x23: ffffff880100da80 x22: 0000000000000000 x21: 0000000000000000 + x20: ffffff8805b14000 x19: ffffff880100da80 x18: 0000000000010450 + x17: 0000000000000000 x16: 0000000000000000 x15: 0000000000000000 + x14: 0000000000000003 x13: 0000000000000000 x12: ffffff880100dad0 + x11: 0000000000000000 x10: ffffffc0832dcd08 x9 : ffffffc0812416d8 + x8 : 00000000000001f4 x7 : ffffffc0830d2830 x6 : 0000000000000001 + x5 : ffffffc082091000 x4 : ffffffc082091658 x3 : 0000000000000000 + x2 : ffffffc7f9653000 x1 : 0000000000000000 x0 : ffffff8802d20000 + Call trace: + crypto_finalize_request+0xa0/0x118 + crypto_finalize_aead_request+0x18/0x30 + zynqmp_handle_aes_req+0xcc/0x388 + crypto_pump_work+0x168/0x2d8 + kthread_worker_fn+0xfc/0x3a0 + kthread+0x118/0x138 + ret_from_fork+0x10/0x20 + irq event stamp: 40 + hardirqs last enabled at (39): [] _raw_spin_unlock_irqrestore+0x70/0xb0 + hardirqs last disabled at (40): [] el1_dbg+0x28/0x90 + softirqs last enabled at (36): [] kernel_neon_begin+0x8c/0xf0 + softirqs last disabled at (34): [] kernel_neon_begin+0x60/0xf0 + ---[ end trace 0000000000000000 ]--- + +Fixes: 4d96f7d48131 ("crypto: xilinx - Add Xilinx AES driver") +Signed-off-by: Quanyang Wang +Signed-off-by: Herbert Xu +Acked-by: Takashi Iwai + +--- + drivers/crypto/xilinx/zynqmp-aes-gcm.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/crypto/xilinx/zynqmp-aes-gcm.c b/drivers/crypto/xilinx/zynqmp-aes-gcm.c +index 3c205324b22b..e61405718840 100644 +--- a/drivers/crypto/xilinx/zynqmp-aes-gcm.c ++++ b/drivers/crypto/xilinx/zynqmp-aes-gcm.c +@@ -231,7 +231,10 @@ static int zynqmp_handle_aes_req(struct crypto_engine *engine, + err = zynqmp_aes_aead_cipher(areq); + } + ++ local_bh_disable(); + crypto_finalize_aead_request(engine, areq, err); ++ local_bh_enable(); ++ + return 0; + } + +-- +2.43.0 + diff --git a/patches.suse/drm-amd-Enable-PCIe-PME-from-D3.patch b/patches.suse/drm-amd-Enable-PCIe-PME-from-D3.patch new file mode 100644 index 0000000..78dcd64 --- /dev/null +++ b/patches.suse/drm-amd-Enable-PCIe-PME-from-D3.patch @@ -0,0 +1,42 @@ +From 6967741d26c87300a51b5e50d4acd104bc1a9759 Mon Sep 17 00:00:00 2001 +From: Mario Limonciello +Date: Fri, 24 Nov 2023 09:56:32 -0600 +Subject: [PATCH] drm/amd: Enable PCIe PME from D3 +Git-commit: 6967741d26c87300a51b5e50d4acd104bc1a9759 +Alt-commit: bd1f6a31e7762ebc99b97f3eda5e5ea3708fa792 +Patch-mainline: v6.7-rc4 +References: git-fixes + +When dGPU is put into BOCO it may be in D3cold but still able send +PME on display hotplug event. For this to work it must be enabled +as wake source from D3. + +When runpm is enabled use pci_wake_from_d3() to mark wakeup as +enabled by default. + +Cc: stable@vger.kernel.org # 6.1+ +Signed-off-by: Mario Limonciello +Acked-by: Alex Deucher +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +index 8f24cabe2155..8b33b130ea36 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +@@ -2263,6 +2263,8 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, + pm_runtime_mark_last_busy(ddev->dev); + pm_runtime_put_autosuspend(ddev->dev); + ++ pci_wake_from_d3(pdev, TRUE); ++ + /* + * For runpm implemented via BACO, PMFW will handle the + * timing for BACO in and out: +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Add-FAMS-validation-before-trying-to.patch b/patches.suse/drm-amd-display-Add-FAMS-validation-before-trying-to.patch new file mode 100644 index 0000000..b2e0e7c --- /dev/null +++ b/patches.suse/drm-amd-display-Add-FAMS-validation-before-trying-to.patch @@ -0,0 +1,77 @@ +From e3416e872f84086667df21daf166506fab97358d Mon Sep 17 00:00:00 2001 +From: Rodrigo Siqueira +Date: Fri, 24 Mar 2023 14:29:52 -0600 +Subject: [PATCH] drm/amd/display: Add FAMS validation before trying to use it +Git-commit: e3416e872f84086667df21daf166506fab97358d +Patch-mainline: v6.5-rc1 +References: git-fixes + +To ensure that FAMS can be used, DC must check if there is VRR support. +This commit adds the required configuration to ensure FAMS can be executed in the target system. + +Reviewed-by: Alvin Lee +Acked-by: Qingqing Zhuo +Signed-off-by: Rodrigo Siqueira +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dc/core/dc.c | 6 ++++++ + drivers/gpu/drm/amd/display/dc/dc_stream.h | 1 + + drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c | 7 ++++++- + drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 2 +- + 4 files changed, 14 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -2630,6 +2630,12 @@ static enum surface_update_type check_up + + if (stream_update->mst_bw_update) + su_flags->bits.mst_bw = 1; ++ ++ if (stream_update->stream && stream_update->stream->freesync_on_desktop && ++ (stream_update->vrr_infopacket || stream_update->allow_freesync || ++ stream_update->vrr_active_variable)) ++ su_flags->bits.fams_changed = 1; ++ + if (stream_update->crtc_timing_adjust && dc_extended_blank_supported(dc)) + su_flags->bits.crtc_timing_adjust = 1; + +--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h ++++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h +@@ -131,6 +131,7 @@ union stream_update_flags { + uint32_t dsc_changed : 1; + uint32_t mst_bw : 1; + uint32_t crtc_timing_adjust : 1; ++ uint32_t fams_changed : 1; + } bits; + + uint32_t raw; +--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c +@@ -292,7 +292,12 @@ void optc3_wait_drr_doublebuffer_pending + + void optc3_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max) + { +- optc1_set_vtotal_min_max(optc, vtotal_min, vtotal_max); ++ struct dc *dc = optc->ctx->dc; ++ ++ if (dc->caps.dmub_caps.mclk_sw && !dc->debug.disable_fams) ++ dc_dmub_srv_drr_update_cmd(dc, optc->inst, vtotal_min, vtotal_max); ++ else ++ optc1_set_vtotal_min_max(optc, vtotal_min, vtotal_max); + } + + void optc3_tg_init(struct timing_generator *optc) +--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h ++++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +@@ -345,7 +345,7 @@ union dmub_fw_boot_status { + uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ + uint32_t restore_required : 1; /**< 1 if driver should call restore */ + uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ +- uint32_t reserved : 1; ++ uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ + uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ + + } bits; /**< status bits */ diff --git a/patches.suse/drm-amd-display-Add-function-for-validate-and-update.patch b/patches.suse/drm-amd-display-Add-function-for-validate-and-update.patch new file mode 100644 index 0000000..b2c6f12 --- /dev/null +++ b/patches.suse/drm-amd-display-Add-function-for-validate-and-update.patch @@ -0,0 +1,330 @@ +From a5e39ae27c3a305c6aafc0e423b0cb2c677facde Mon Sep 17 00:00:00 2001 +From: Rodrigo Siqueira +Date: Tue, 18 Oct 2022 08:28:21 -0400 +Subject: [PATCH] drm/amd/display: Add function for validate and update new stream +Git-commit: a5e39ae27c3a305c6aafc0e423b0cb2c677facde +Patch-mainline: v6.2-rc1 +References: git-fixes + +DC stream can be seen as a representation of the DCN backend or the data +struct that represents the center of the display pipeline. The front end +(i.e., planes) is connected to the DC stream, and in its turn, streams +are connected to the DC link. Due to this dynamic, DC must handle the +following scenarios: + +1. A stream is removed; +2. A new stream is created; +3. An unchanged stream had some updates on its planes. + +These combinations require that the new stream data struct become +updated and has a valid global state. For handling multiple corner cases +associated with stream operations, this commit introduces a function +dedicated to manipulating stream changes and invokes the state +validation function after that. + +Reviewed-by: Harry Wentland +Signed-off-by: Rodrigo Siqueira +Co-developed-by: Aurabindo Pillai +Signed-off-by: Aurabindo Pillai +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dc/core/dc.c | 16 +- + .../gpu/drm/amd/display/dc/core/dc_resource.c | 219 +++++++++++++++++- + drivers/gpu/drm/amd/display/dc/dc.h | 6 + + 3 files changed, 227 insertions(+), 14 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index 61b574b9e736..d568387c4bda 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -1941,21 +1941,17 @@ enum dc_status dc_commit_streams(struct dc *dc, + + dc_resource_state_copy_construct_current(dc, context); + +- /* +- * Previous validation was perfomred with fast_validation = true and +- * the full DML state required for hardware programming was skipped. +- * +- * Re-validate here to calculate these parameters / watermarks. +- */ +- res = dc_validate_global_state(dc, context, false); ++ res = dc_validate_with_context(dc, set, stream_count, context, false); + if (res != DC_OK) { +- DC_LOG_ERROR("DC commit global validation failure: %s (%d)", +- dc_status_to_str(res), res); +- return res; ++ BREAK_TO_DEBUGGER(); ++ goto fail; + } + + res = dc_commit_state_no_check(dc, context); + ++fail: ++ dc_release_state(context); ++ + context_alloc_fail: + + DC_LOG_DC("%s Finished.\n", __func__); +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +index fd8db482e56f..e001b138b2ac 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +@@ -2593,15 +2593,226 @@ bool dc_resource_is_dsc_encoding_supported(const struct dc *dc) + return dc->res_pool->res_cap->num_dsc > 0; + } + ++static bool planes_changed_for_existing_stream(struct dc_state *context, ++ struct dc_stream_state *stream, ++ const struct dc_validation_set set[], ++ int set_count) ++{ ++ int i, j; ++ struct dc_stream_status *stream_status = NULL; ++ ++ for (i = 0; i < context->stream_count; i++) { ++ if (context->streams[i] == stream) { ++ stream_status = &context->stream_status[i]; ++ break; ++ } ++ } ++ ++ if (!stream_status) ++ ASSERT(0); ++ ++ for (i = 0; i < set_count; i++) ++ if (set[i].stream == stream) ++ break; ++ ++ if (i == set_count) ++ ASSERT(0); ++ ++ if (set[i].plane_count != stream_status->plane_count) ++ return true; ++ ++ for (j = 0; j < set[i].plane_count; j++) ++ if (set[i].plane_states[j] != stream_status->plane_states[j]) ++ return true; ++ ++ return false; ++} + + /** +- * dc_validate_global_state() - Determine if HW can support a given state +- * Checks HW resource availability and bandwidth requirement. ++ * dc_validate_with_context - Validate and update the potential new stream in the context object ++ * ++ * @dc: Used to get the current state status ++ * @set: An array of dc_validation_set with all the current streams reference ++ * @set_count: Total of streams ++ * @context: New context ++ * @fast_validate: Enable or disable fast validation ++ * ++ * This function updates the potential new stream in the context object. It ++ * creates multiple lists for the add, remove, and unchanged streams. In ++ * particular, if the unchanged streams have a plane that changed, it is ++ * necessary to remove all planes from the unchanged streams. In summary, this ++ * function is responsible for validating the new context. ++ * ++ * Return: ++ * In case of success, return DC_OK (1), otherwise, return a DC error. ++ */ ++enum dc_status dc_validate_with_context(struct dc *dc, ++ const struct dc_validation_set set[], ++ int set_count, ++ struct dc_state *context, ++ bool fast_validate) ++{ ++ struct dc_stream_state *unchanged_streams[MAX_PIPES] = { 0 }; ++ struct dc_stream_state *del_streams[MAX_PIPES] = { 0 }; ++ struct dc_stream_state *add_streams[MAX_PIPES] = { 0 }; ++ int old_stream_count = context->stream_count; ++ enum dc_status res = DC_ERROR_UNEXPECTED; ++ int unchanged_streams_count = 0; ++ int del_streams_count = 0; ++ int add_streams_count = 0; ++ bool found = false; ++ int i, j, k; ++ ++ DC_LOGGER_INIT(dc->ctx->logger); ++ ++ /* First build a list of streams to be remove from current context */ ++ for (i = 0; i < old_stream_count; i++) { ++ struct dc_stream_state *stream = context->streams[i]; ++ ++ for (j = 0; j < set_count; j++) { ++ if (stream == set[j].stream) { ++ found = true; ++ break; ++ } ++ } ++ ++ if (!found) ++ del_streams[del_streams_count++] = stream; ++ ++ found = false; ++ } ++ ++ /* Second, build a list of new streams */ ++ for (i = 0; i < set_count; i++) { ++ struct dc_stream_state *stream = set[i].stream; ++ ++ for (j = 0; j < old_stream_count; j++) { ++ if (stream == context->streams[j]) { ++ found = true; ++ break; ++ } ++ } ++ ++ if (!found) ++ add_streams[add_streams_count++] = stream; ++ ++ found = false; ++ } ++ ++ /* Build a list of unchanged streams which is necessary for handling ++ * planes change such as added, removed, and updated. ++ */ ++ for (i = 0; i < set_count; i++) { ++ /* Check if stream is part of the delete list */ ++ for (j = 0; j < del_streams_count; j++) { ++ if (set[i].stream == del_streams[j]) { ++ found = true; ++ break; ++ } ++ } ++ ++ if (!found) { ++ /* Check if stream is part of the add list */ ++ for (j = 0; j < add_streams_count; j++) { ++ if (set[i].stream == add_streams[j]) { ++ found = true; ++ break; ++ } ++ } ++ } ++ ++ if (!found) ++ unchanged_streams[unchanged_streams_count++] = set[i].stream; ++ ++ found = false; ++ } ++ ++ /* Remove all planes for unchanged streams if planes changed */ ++ for (i = 0; i < unchanged_streams_count; i++) { ++ if (planes_changed_for_existing_stream(context, ++ unchanged_streams[i], ++ set, ++ set_count)) { ++ if (!dc_rem_all_planes_for_stream(dc, ++ unchanged_streams[i], ++ context)) { ++ res = DC_FAIL_DETACH_SURFACES; ++ goto fail; ++ } ++ } ++ } ++ ++ /* Remove all planes for removed streams and then remove the streams */ ++ for (i = 0; i < del_streams_count; i++) { ++ /* Need to cpy the dwb data from the old stream in order to efc to work */ ++ if (del_streams[i]->num_wb_info > 0) { ++ for (j = 0; j < add_streams_count; j++) { ++ if (del_streams[i]->sink == add_streams[j]->sink) { ++ add_streams[j]->num_wb_info = del_streams[i]->num_wb_info; ++ for (k = 0; k < del_streams[i]->num_wb_info; k++) ++ add_streams[j]->writeback_info[k] = del_streams[i]->writeback_info[k]; ++ } ++ } ++ } ++ ++ if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) { ++ res = DC_FAIL_DETACH_SURFACES; ++ goto fail; ++ } ++ ++ res = dc_remove_stream_from_ctx(dc, context, del_streams[i]); ++ if (res != DC_OK) ++ goto fail; ++ } ++ ++ /* Add new streams and then add all planes for the new stream */ ++ for (i = 0; i < add_streams_count; i++) { ++ calculate_phy_pix_clks(add_streams[i]); ++ res = dc_add_stream_to_ctx(dc, context, add_streams[i]); ++ if (res != DC_OK) ++ goto fail; ++ ++ if (!add_all_planes_for_stream(dc, add_streams[i], set, set_count, context)) { ++ res = DC_FAIL_ATTACH_SURFACES; ++ goto fail; ++ } ++ } ++ ++ /* Add all planes for unchanged streams if planes changed */ ++ for (i = 0; i < unchanged_streams_count; i++) { ++ if (planes_changed_for_existing_stream(context, ++ unchanged_streams[i], ++ set, ++ set_count)) { ++ if (!add_all_planes_for_stream(dc, unchanged_streams[i], set, set_count, context)) { ++ res = DC_FAIL_ATTACH_SURFACES; ++ goto fail; ++ } ++ } ++ } ++ ++ res = dc_validate_global_state(dc, context, fast_validate); ++ ++fail: ++ if (res != DC_OK) ++ DC_LOG_WARNING("%s:resource validation failed, dc_status:%d\n", ++ __func__, ++ res); ++ ++ return res; ++} ++ ++/** ++ * dc_validate_global_state() - Determine if hardware can support a given state ++ * + * @dc: dc struct for this driver + * @new_ctx: state to be validated + * @fast_validate: set to true if only yes/no to support matters + * +- * Return: DC_OK if the result can be programmed. Otherwise, an error code. ++ * Checks hardware resource availability and bandwidth requirement. ++ * ++ * Return: ++ * DC_OK if the result can be programmed. Otherwise, an error code. + */ + enum dc_status dc_validate_global_state( + struct dc *dc, +@@ -3734,4 +3945,4 @@ bool dc_resource_acquire_secondary_pipe_for_mpc_odm( + } + + return true; +-} +\ No newline at end of file ++} +diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h +index 836cdf5d4114..bf938cda379a 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc.h ++++ b/drivers/gpu/drm/amd/display/dc/dc.h +@@ -1297,6 +1297,12 @@ enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *pla + + void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); + ++enum dc_status dc_validate_with_context(struct dc *dc, ++ const struct dc_validation_set set[], ++ int set_count, ++ struct dc_state *context, ++ bool fast_validate); ++ + bool dc_set_generic_gpio_for_stereo(bool enable, + struct gpio_service *gpio_service); + +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Avoid-ABM-when-ODM-combine-is-enable.patch b/patches.suse/drm-amd-display-Avoid-ABM-when-ODM-combine-is-enable.patch new file mode 100644 index 0000000..b67a170 --- /dev/null +++ b/patches.suse/drm-amd-display-Avoid-ABM-when-ODM-combine-is-enable.patch @@ -0,0 +1,51 @@ +From 7fffb03b4045c862f904a88b852dc509c4e46406 Mon Sep 17 00:00:00 2001 +From: Rodrigo Siqueira +Date: Tue, 18 Oct 2022 08:28:24 -0400 +Subject: [PATCH] drm/amd/display: Avoid ABM when ODM combine is enabled for eDP +Git-commit: 7fffb03b4045c862f904a88b852dc509c4e46406 +Patch-mainline: v6.2-rc1 +References: git-fixes + +ODM to combine on the eDP panel with ABM causes the color difference to +the panel since the ABM module only sets one pipe. Hence, this commit +blocks ABM in case of ODM combined on eDP. + +Reviewed-by: Harry Wentland +Signed-off-by: Rodrigo Siqueira +Co-developed-by: Aurabindo Pillai +Signed-off-by: Aurabindo Pillai +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dc/core/dc.c | 12 +++++++++++- + 1 file changed, 11 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index b7afada35b24..375439c51cd3 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -1950,9 +1950,19 @@ enum dc_status dc_commit_streams(struct dc *dc, + res = dc_commit_state_no_check(dc, context); + + for (i = 0; i < stream_count; i++) { +- for (j = 0; j < context->stream_count; j++) ++ for (j = 0; j < context->stream_count; j++) { + if (streams[i]->stream_id == context->streams[j]->stream_id) + streams[i]->out.otg_offset = context->stream_status[j].primary_otg_inst; ++ ++ if (dc_is_embedded_signal(streams[i]->signal)) { ++ struct dc_stream_status *status = dc_stream_get_status_from_state(context, streams[i]); ++ ++ if (dc->hwss.is_abm_supported) ++ status->is_abm_supported = dc->hwss.is_abm_supported(dc, context, streams[i]); ++ else ++ status->is_abm_supported = true; ++ } ++ } + } + + fail: +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Blocking-invalid-420-modes-on-HDMI-T.patch b/patches.suse/drm-amd-display-Blocking-invalid-420-modes-on-HDMI-T.patch new file mode 100644 index 0000000..634b748 --- /dev/null +++ b/patches.suse/drm-amd-display-Blocking-invalid-420-modes-on-HDMI-T.patch @@ -0,0 +1,42 @@ +From 026a71babf48efb6b9884a3a66fa31aec9e1ea54 Mon Sep 17 00:00:00 2001 +From: Leo Chen +Date: Mon, 24 Jul 2023 16:57:36 -0400 +Subject: [PATCH] drm/amd/display: Blocking invalid 420 modes on HDMI TMDS for DCN31 +Git-commit: 026a71babf48efb6b9884a3a66fa31aec9e1ea54 +Patch-mainline: v6.6-rc1 +References: git-fixes + +[Why & How] +HDMI TMDS does not have ODM support. Filtering 420 modes that +exceed the 4096 FMT limitation on DCN31 will resolve +intermittent corruptions issues. + +Reviewed-by: Nicholas Kazlauskas +Acked-by: Tom Chung +Signed-off-by: Leo Chen +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + .../gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c +index eba51144fee7..adea459e7d36 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c +@@ -4135,7 +4135,9 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l + } + if (v->OutputFormat[k] == dm_420 && v->HActive[k] > DCN31_MAX_FMT_420_BUFFER_WIDTH + && v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) { +- if (v->HActive[k] / 2 > DCN31_MAX_FMT_420_BUFFER_WIDTH) { ++ if (v->Output[k] == dm_hdmi) { ++ FMTBufferExceeded = true; ++ } else if (v->HActive[k] / 2 > DCN31_MAX_FMT_420_BUFFER_WIDTH) { + v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1; + v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine4To1; + +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Check-if-link-state-is-valid.patch b/patches.suse/drm-amd-display-Check-if-link-state-is-valid.patch new file mode 100644 index 0000000..c68af85 --- /dev/null +++ b/patches.suse/drm-amd-display-Check-if-link-state-is-valid.patch @@ -0,0 +1,39 @@ +From 03ce7b387e8b0f4a1dc97a878545bdf7c7f23251 Mon Sep 17 00:00:00 2001 +From: Rodrigo Siqueira +Date: Tue, 18 Oct 2022 08:28:15 -0400 +Subject: [PATCH] drm/amd/display: Check if link state is valid +Git-commit: 03ce7b387e8b0f4a1dc97a878545bdf7c7f23251 +Patch-mainline: v6.2-rc1 +References: git-fixes + +The link state is set to false if there is no link and local sink. Even +though the stream state may not change, it is desirable to commit the +new stream when HPD goes low to high. + +Reviewed-by: Harry Wentland +Signed-off-by: Rodrigo Siqueira +Co-developed-by: Aurabindo Pillai +Signed-off-by: Aurabindo Pillai +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dc/core/dc.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index 997ab031f816..7b576bd24cb5 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -1500,6 +1500,8 @@ static bool context_changed( + for (i = 0; i < dc->current_state->stream_count; i++) { + if (dc->current_state->streams[i] != context->streams[i]) + return true; ++ if (!context->streams[i]->link->link_state_valid) ++ return true; + } + + return false; +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Copy-DC-context-in-the-commit-stream.patch b/patches.suse/drm-amd-display-Copy-DC-context-in-the-commit-stream.patch new file mode 100644 index 0000000..165bd25 --- /dev/null +++ b/patches.suse/drm-amd-display-Copy-DC-context-in-the-commit-stream.patch @@ -0,0 +1,121 @@ +From 0e986cea0347902b2c72b09c8fe9c0f30d7decb4 Mon Sep 17 00:00:00 2001 +From: Rodrigo Siqueira +Date: Tue, 18 Oct 2022 08:28:18 -0400 +Subject: [PATCH] drm/amd/display: Copy DC context in the commit streams +Git-commit: 0e986cea0347902b2c72b09c8fe9c0f30d7decb4 +Patch-mainline: v6.2-rc1 +References: git-fixes + +DC adds an instance of DML (which contains VBA) to each context, and +multiple threads might write back to the global VBA resulting in data +overwriting. To keep the consistency with other parts of the DC code, +this commit changes dc_commit_streams to copy the current DC state, and +as a result, it also changes the function signature to expect streams +instead of a context. + +Reviewed-by: Harry Wentland +Signed-off-by: Rodrigo Siqueira +Co-developed-by: Aurabindo Pillai +Signed-off-by: Aurabindo Pillai +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dc/core/dc.c | 41 +++++++++++++++++++----- + drivers/gpu/drm/amd/display/dc/dc.h | 4 ++- + 2 files changed, 36 insertions(+), 9 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index 5d9e9e8f87d3..af81c2835738 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -1890,23 +1890,44 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c + return result; + } + +-enum dc_status dc_commit_streams(struct dc *dc, struct dc_state *context) ++/** ++ * dc_commit_streams - Commit current stream state ++ * ++ * @dc: DC object with the commit state to be configured in the hardware ++ * @streams: Array with a list of stream state ++ * @stream_count: Total of streams ++ * ++ * Function responsible for commit streams change to the hardware. ++ * ++ * Return: ++ * Return DC_OK if everything work as expected, otherwise, return a dc_status ++ * code. ++ */ ++enum dc_status dc_commit_streams(struct dc *dc, ++ struct dc_stream_state *streams[], ++ uint8_t stream_count) + { +- enum dc_status res = DC_OK; + int i; ++ struct dc_state *context; ++ enum dc_status res = DC_OK; + +- if (!streams_changed(dc, context->streams, context->stream_count)) ++ if (!streams_changed(dc, streams, stream_count)) + return res; + +- DC_LOG_DC("%s: %d streams\n", +- __func__, context->stream_count); ++ DC_LOG_DC("%s: %d streams\n", __func__, stream_count); + +- for (i = 0; i < context->stream_count; i++) { +- struct dc_stream_state *stream = context->streams[i]; ++ for (i = 0; i < stream_count; i++) { ++ struct dc_stream_state *stream = streams[i]; + + dc_stream_log(dc, stream); + } + ++ context = dc_create_state(dc); ++ if (!context) ++ goto context_alloc_fail; ++ ++ dc_resource_state_copy_construct_current(dc, context); ++ + /* + * Previous validation was perfomred with fast_validation = true and + * the full DML state required for hardware programming was skipped. +@@ -1922,6 +1943,10 @@ enum dc_status dc_commit_streams(struct dc *dc, struct dc_state *context) + + res = dc_commit_state_no_check(dc, context); + ++context_alloc_fail: ++ ++ DC_LOG_DC("%s Finished.\n", __func__); ++ + return (res == DC_OK); + } + +@@ -1937,7 +1962,7 @@ bool dc_commit_state(struct dc *dc, struct dc_state *context) + * we get more confident about this change we'll need to enable + * the new sequence for all ASICs. */ + if (dc->ctx->dce_version >= DCN_VERSION_3_2) { +- result = dc_commit_streams(dc, context); ++ result = dc_commit_streams(dc, context->streams, context->stream_count); + return result == DC_OK; + } + +diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h +index 2e71781f155b..6adecb62e534 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc.h ++++ b/drivers/gpu/drm/amd/display/dc/dc.h +@@ -1321,7 +1321,9 @@ void dc_resource_state_destruct(struct dc_state *context); + + bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); + +-enum dc_status dc_commit_streams(struct dc *dc, struct dc_state *context); ++enum dc_status dc_commit_streams(struct dc *dc, ++ struct dc_stream_state *streams[], ++ uint8_t stream_count); + + /* TODO: When the transition to the new commit sequence is done, remove this + * function in favor of dc_commit_streams. */ +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Disable-PSR-SU-on-Parade-0803-TCON-a.patch b/patches.suse/drm-amd-display-Disable-PSR-SU-on-Parade-0803-TCON-a.patch new file mode 100644 index 0000000..4655424 --- /dev/null +++ b/patches.suse/drm-amd-display-Disable-PSR-SU-on-Parade-0803-TCON-a.patch @@ -0,0 +1,54 @@ +From e7ab758741672acb21c5d841a9f0309d30e48a06 Mon Sep 17 00:00:00 2001 +From: Mario Limonciello +Date: Mon, 19 Jun 2023 15:04:24 -0500 +Subject: [PATCH] drm/amd/display: Disable PSR-SU on Parade 0803 TCON again +Git-commit: e7ab758741672acb21c5d841a9f0309d30e48a06 +Alt-commit: 571c2fa26aa654946447c282a09d40a56c7ff128 +Patch-mainline: v6.7-rc6 +References: git-fixes + +When screen brightness is rapidly changed and PSR-SU is enabled the +display hangs on panels with this TCON even on the latest DCN 3.1.4 +microcode (0x8002a81 at this time). + +This was disabled previously as commit 072030b17830 ("drm/amd: Disable +PSR-SU on Parade 0803 TCON") but reverted as commit 1e66a17ce546 ("Revert +"drm/amd: Disable PSR-SU on Parade 0803 TCON"") in favor of testing for +a new enough microcode (commit cd2e31a9ab93 ("drm/amd/display: Set minimum +requirement for using PSR-SU on Phoenix")). + +As hangs are still happening specifically with this TCON, disable PSR-SU +again for it until it can be root caused. + +Cc: stable@vger.kernel.org +Cc: aaron.ma@canonical.com +Cc: binli@gnome.org +Cc: Marc Rossi +Cc: Hamza Mahfooz +Signed-off-by: Mario Limonciello +Link: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/2046131 +Acked-by: Alex Deucher +Reviewed-by: Harry Wentland +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/modules/power/power_helpers.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c +index a522a7c02911..1675314a3ff2 100644 +--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c ++++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c +@@ -839,6 +839,8 @@ bool is_psr_su_specific_panel(struct dc_link *link) + ((dpcd_caps->sink_dev_id_str[1] == 0x08 && dpcd_caps->sink_dev_id_str[0] == 0x08) || + (dpcd_caps->sink_dev_id_str[1] == 0x08 && dpcd_caps->sink_dev_id_str[0] == 0x07))) + isPSRSUSupported = false; ++ else if (dpcd_caps->sink_dev_id_str[1] == 0x08 && dpcd_caps->sink_dev_id_str[0] == 0x03) ++ isPSRSUSupported = false; + else if (dpcd_caps->psr_info.force_psrsu_cap == 0x1) + isPSRSUSupported = true; + } +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Enable-fast-plane-updates-on-DCN3.2-.patch b/patches.suse/drm-amd-display-Enable-fast-plane-updates-on-DCN3.2-.patch new file mode 100644 index 0000000..d2b9077 --- /dev/null +++ b/patches.suse/drm-amd-display-Enable-fast-plane-updates-on-DCN3.2-.patch @@ -0,0 +1,56 @@ +From 435f5b369657cffee4b04db1f5805b48599f4dbe Mon Sep 17 00:00:00 2001 +From: Tianci Yin +Date: Wed, 1 Nov 2023 09:47:13 +0800 +Subject: [PATCH] drm/amd/display: Enable fast plane updates on DCN3.2 and above +Git-commit: 435f5b369657cffee4b04db1f5805b48599f4dbe +Patch-mainline: v6.7-rc2 +References: git-fixes + +[WHY] +When cursor moves across screen boarder, lag cursor observed, +since subvp settings need to sync up with vblank that causes +cursor updates being delayed. + +[HOW] +Enable fast plane updates on DCN3.2 to fix it. + +Cc: Mario Limonciello +Cc: Alex Deucher +Cc: stable@vger.kernel.org +Reviewed-by: Aurabindo Pillai +Acked-by: Alex Hung +Signed-off-by: Tianci Yin +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +index 5ec7acf65ee1..9581510d3740 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -9606,14 +9606,14 @@ static bool should_reset_plane(struct drm_atomic_state *state, + struct drm_plane *other; + struct drm_plane_state *old_other_state, *new_other_state; + struct drm_crtc_state *new_crtc_state; ++ struct amdgpu_device *adev = drm_to_adev(plane->dev); + int i; + + /* +- * TODO: Remove this hack once the checks below are sufficient +- * enough to determine when we need to reset all the planes on +- * the stream. ++ * TODO: Remove this hack for all asics once it proves that the ++ * fast updates works fine on DCN3.2+. + */ +- if (state->allow_modeset) ++ if (adev->ip_versions[DCE_HWIP][0] < IP_VERSION(3, 2, 0) && state->allow_modeset) + return true; + + /* Exit early if we know that we're adding or removing the plane. */ +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Enable-new-commit-sequence-only-for-.patch b/patches.suse/drm-amd-display-Enable-new-commit-sequence-only-for-.patch new file mode 100644 index 0000000..097cff6 --- /dev/null +++ b/patches.suse/drm-amd-display-Enable-new-commit-sequence-only-for-.patch @@ -0,0 +1,119 @@ +From 7b36f4d18e3e4941d12fe027ad6ad6123c257027 Mon Sep 17 00:00:00 2001 +From: Rodrigo Siqueira +Date: Tue, 18 Oct 2022 08:28:17 -0400 +Subject: [PATCH] drm/amd/display: Enable new commit sequence only for DCN32x +Git-commit: 7b36f4d18e3e4941d12fe027ad6ad6123c257027 +Patch-mainline: v6.2-rc1 +References: git-fixes + +Change commit sequence will impact all ASICs. It is prudent to run this +update in small steps to keep issues under control and avoid any +potential regression. With this idea in mind, this commit is preparation +work for the complete transition to the new commit sequence. To maintain +this change manageable across multiple ASICs, this commit adds a new +function named dc_commit_streams which is a copy of the dc_commit_state +with some minor changes. Finally, inside the dc_commit_state, we check +if we are using DCN32x or above and enable the new sequence only for +those devices. + +Reviewed-by: Harry Wentland +Signed-off-by: Rodrigo Siqueira +Co-developed-by: Aurabindo Pillai +Signed-off-by: Aurabindo Pillai +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dc/core/dc.c | 46 ++++++++++++++++++++++++ + drivers/gpu/drm/amd/display/dc/dc.h | 13 +++---- + 2 files changed, 50 insertions(+), 9 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index 9219d1efde2a..5d9e9e8f87d3 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -1890,11 +1890,57 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c + return result; + } + ++enum dc_status dc_commit_streams(struct dc *dc, struct dc_state *context) ++{ ++ enum dc_status res = DC_OK; ++ int i; ++ ++ if (!streams_changed(dc, context->streams, context->stream_count)) ++ return res; ++ ++ DC_LOG_DC("%s: %d streams\n", ++ __func__, context->stream_count); ++ ++ for (i = 0; i < context->stream_count; i++) { ++ struct dc_stream_state *stream = context->streams[i]; ++ ++ dc_stream_log(dc, stream); ++ } ++ ++ /* ++ * Previous validation was perfomred with fast_validation = true and ++ * the full DML state required for hardware programming was skipped. ++ * ++ * Re-validate here to calculate these parameters / watermarks. ++ */ ++ res = dc_validate_global_state(dc, context, false); ++ if (res != DC_OK) { ++ DC_LOG_ERROR("DC commit global validation failure: %s (%d)", ++ dc_status_to_str(res), res); ++ return res; ++ } ++ ++ res = dc_commit_state_no_check(dc, context); ++ ++ return (res == DC_OK); ++} ++ ++/* TODO: When the transition to the new commit sequence is done, remove this ++ * function in favor of dc_commit_streams. */ + bool dc_commit_state(struct dc *dc, struct dc_state *context) + { + enum dc_status result = DC_ERROR_UNEXPECTED; + int i; + ++ /* TODO: Since change commit sequence can have a huge impact, ++ * we decided to only enable it for DCN3x. However, as soon as ++ * we get more confident about this change we'll need to enable ++ * the new sequence for all ASICs. */ ++ if (dc->ctx->dce_version >= DCN_VERSION_3_2) { ++ result = dc_commit_streams(dc, context); ++ return result == DC_OK; ++ } ++ + if (!streams_changed(dc, context->streams, context->stream_count)) + return DC_OK; + +diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h +index bfc5474c0f4c..2e71781f155b 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc.h ++++ b/drivers/gpu/drm/amd/display/dc/dc.h +@@ -1321,15 +1321,10 @@ void dc_resource_state_destruct(struct dc_state *context); + + bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); + +-/* +- * TODO update to make it about validation sets +- * Set up streams and links associated to drive sinks +- * The streams parameter is an absolute set of all active streams. +- * +- * After this call: +- * Phy, Encoder, Timing Generator are programmed and enabled. +- * New streams are enabled with blank stream; no memory read. +- */ ++enum dc_status dc_commit_streams(struct dc *dc, struct dc_state *context); ++ ++/* TODO: When the transition to the new commit sequence is done, remove this ++ * function in favor of dc_commit_streams. */ + bool dc_commit_state(struct dc *dc, struct dc_state *context); + + struct dc_state *dc_create_state(struct dc *dc); +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Exit-idle-optimizations-before-attem.patch b/patches.suse/drm-amd-display-Exit-idle-optimizations-before-attem.patch new file mode 100644 index 0000000..df282e2 --- /dev/null +++ b/patches.suse/drm-amd-display-Exit-idle-optimizations-before-attem.patch @@ -0,0 +1,45 @@ +From de612738e9771bd66aeb20044486c457c512f684 Mon Sep 17 00:00:00 2001 +From: Leo Chen +Date: Wed, 12 Jul 2023 16:50:15 -0400 +Subject: [PATCH] drm/amd/display: Exit idle optimizations before attempt to access PHY +Git-commit: de612738e9771bd66aeb20044486c457c512f684 +Patch-mainline: v6.5-rc4 +References: git-fixes + +[Why & How] +DMUB may hang when powering down pixel clocks due to no dprefclk. + +It is fixed by exiting idle optimization before the attempt to access PHY. + +Reviewed-by: Nicholas Kazlauskas +Acked-by: Alex Hung +Signed-off-by: Leo Chen +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +index 6c9ca43d1040..20d4d08a6a2f 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +@@ -1792,10 +1792,13 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) + hws->funcs.edp_backlight_control(edp_link_with_sink, false); + } + /*resume from S3, no vbios posting, no need to power down again*/ ++ clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr); ++ + power_down_all_hw_blocks(dc); + disable_vga_and_power_gate_all_controllers(dc); + if (edp_link_with_sink && !keep_edp_vdd_on) + dc->hwss.edp_power_control(edp_link_with_sink, false); ++ clk_mgr_optimize_pwr_state(dc, dc->clk_mgr); + } + bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 1); + } +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Expand-kernel-doc-for-DC.patch b/patches.suse/drm-amd-display-Expand-kernel-doc-for-DC.patch new file mode 100644 index 0000000..33e4ce7 --- /dev/null +++ b/patches.suse/drm-amd-display-Expand-kernel-doc-for-DC.patch @@ -0,0 +1,208 @@ +From 1682bd1a6b5fb094e914d9b73b711821fd84dcbd Mon Sep 17 00:00:00 2001 +From: Rodrigo Siqueira +Date: Thu, 20 Oct 2022 11:46:57 -0400 +Subject: [PATCH] drm/amd/display: Expand kernel doc for DC +Git-commit: 1682bd1a6b5fb094e914d9b73b711821fd84dcbd +Patch-mainline: v6.2-rc1 +References: git-fixes + +This commit adds extra documentation for elements related to FAMs. + +Tested-by: Mark Broadworth +Reviewed-by: Aurabindo Pillai +Acked-by: Rodrigo Siqueira +Signed-off-by: Rodrigo Siqueira +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dc/dc.h | 19 +++++++++++--- + drivers/gpu/drm/amd/display/dc/dc_stream.h | 11 ++++++++ + .../gpu/drm/amd/display/dc/dml/dc_features.h | 7 ++++++ + .../amd/display/dc/dml/display_mode_enums.h | 25 +++++++++++++++++++ + .../drm/amd/display/dc/dml/display_mode_vba.h | 9 +++++++ + .../gpu/drm/amd/display/dc/inc/core_types.h | 7 ++++++ + .../gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 7 ++++++ + 7 files changed, 82 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h +index 3450aca538b5..44f8db160520 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc.h ++++ b/drivers/gpu/drm/amd/display/dc/dc.h +@@ -494,9 +494,12 @@ enum dcn_zstate_support_state { + DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, + DCN_ZSTATE_SUPPORT_DISALLOW, + }; +-/* +- * For any clocks that may differ per pipe +- * only the max is stored in this structure ++ ++/** ++ * dc_clocks - DC pipe clocks ++ * ++ * For any clocks that may differ per pipe only the max is stored in this ++ * structure + */ + struct dc_clocks { + int dispclk_khz; +@@ -523,6 +526,16 @@ struct dc_clocks { + bool prev_p_state_change_support; + bool fclk_prev_p_state_change_support; + int num_ways; ++ ++ /** ++ * @fw_based_mclk_switching ++ * ++ * DC has a mechanism that leverage the variable refresh rate to switch ++ * memory clock in cases that we have a large latency to achieve the ++ * memory clock change and a short vblank window. DC has some ++ * requirements to enable this feature, and this field describes if the ++ * system support or not such a feature. ++ */ + bool fw_based_mclk_switching; + bool fw_based_mclk_switching_shut_down; + int prev_num_ways; +diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h +index 4d30ae0ca721..f4dfd3a49b68 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h ++++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h +@@ -201,7 +201,18 @@ struct dc_stream_state { + bool use_vsc_sdp_for_colorimetry; + bool ignore_msa_timing_param; + ++ /** ++ * @allow_freesync: ++ * ++ * It say if Freesync is enabled or not. ++ */ + bool allow_freesync; ++ ++ /** ++ * @vrr_active_variable: ++ * ++ * It describes if VRR is in use. ++ */ + bool vrr_active_variable; + bool freesync_on_desktop; + +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dc_features.h b/drivers/gpu/drm/amd/display/dc/dml/dc_features.h +index 74e86732e301..2cbdd75429ff 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dc_features.h ++++ b/drivers/gpu/drm/amd/display/dc/dml/dc_features.h +@@ -29,6 +29,13 @@ + #define DC__PRESENT 1 + #define DC__PRESENT__1 1 + #define DC__NUM_DPP 4 ++ ++/** ++ * @DC__VOLTAGE_STATES: ++ * ++ * Define the maximum amount of states supported by the ASIC. Every ASIC has a ++ * specific number of states; this macro defines the maximum number of states. ++ */ + #define DC__VOLTAGE_STATES 20 + #define DC__NUM_DPP__4 1 + #define DC__NUM_DPP__0_PRESENT 1 +diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h +index f394b3f3922a..0bffae95f3a2 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h ++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h +@@ -105,14 +105,39 @@ enum source_macro_tile_size { + enum cursor_bpp { + dm_cur_2bit = 0, dm_cur_32bit = 1, dm_cur_64bit = 2 + }; ++ ++/** ++ * @enum clock_change_support - It represents possible reasons to change the DRAM clock. ++ * ++ * DC may change the DRAM clock during its execution, and this enum tracks all ++ * the available methods. Note that every ASIC has their specific way to deal ++ * with these clock switch. ++ */ + enum clock_change_support { ++ /** ++ * @dm_dram_clock_change_uninitialized: If you see this, we might have ++ * a code initialization issue ++ */ + dm_dram_clock_change_uninitialized = 0, ++ ++ /** ++ * @dm_dram_clock_change_vactive: Support DRAM switch in VActive ++ */ + dm_dram_clock_change_vactive, ++ ++ /** ++ * @dm_dram_clock_change_vblank: Support DRAM switch in VBlank ++ */ + dm_dram_clock_change_vblank, ++ + dm_dram_clock_change_vactive_w_mall_full_frame, + dm_dram_clock_change_vactive_w_mall_sub_vp, + dm_dram_clock_change_vblank_w_mall_full_frame, + dm_dram_clock_change_vblank_w_mall_sub_vp, ++ ++ /** ++ * @dm_dram_clock_change_unsupported: Do not support DRAM switch ++ */ + dm_dram_clock_change_unsupported + }; + +diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h +index 630f3395e90a..d46aa4817e70 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h ++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h +@@ -419,6 +419,15 @@ struct vba_vars_st { + double MinPixelChunkSizeBytes; + unsigned int DCCMetaBufferSizeBytes; + // Pipe/Plane Parameters ++ ++ /** @VoltageLevel: ++ * Every ASIC has a fixed number of DPM states, and some devices might ++ * have some particular voltage configuration that does not map ++ * directly to the DPM states. This field tells how many states the ++ * target device supports; even though this field combines the DPM and ++ * special SOC voltages, it mostly matches the total number of DPM ++ * states. ++ */ + int VoltageLevel; + double FabricClock; + double DRAMSpeed; +diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h +index 9498105c98ab..295845d49cb9 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h +@@ -115,6 +115,13 @@ struct resource_funcs { + int vlevel); + void (*update_soc_for_wm_a)( + struct dc *dc, struct dc_state *context); ++ ++ /** ++ * @populate_dml_pipes - Populate pipe data struct ++ * ++ * Returns: ++ * Total of pipes available in the specific ASIC. ++ */ + int (*populate_dml_pipes)( + struct dc *dc, + struct dc_state *context, +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +index cd2be729846b..a819f0f97c5f 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +@@ -35,6 +35,13 @@ + ******************************************************************************/ + + #define MAX_AUDIOS 7 ++ ++/** ++ * @MAX_PIPES: ++ * ++ * Every ASIC support a fixed number of pipes; MAX_PIPES defines a large number ++ * to be used inside loops and for determining array sizes. ++ */ + #define MAX_PIPES 6 + #define MAX_DIG_LINK_ENCODERS 7 + #define MAX_DWB_PIPES 1 +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Fix-a-bug-when-searching-for-insert_.patch b/patches.suse/drm-amd-display-Fix-a-bug-when-searching-for-insert_.patch new file mode 100644 index 0000000..4a383cd --- /dev/null +++ b/patches.suse/drm-amd-display-Fix-a-bug-when-searching-for-insert_.patch @@ -0,0 +1,48 @@ +From 3d028d5d60d516c536de1ddd3ebf3d55f3f8983b Mon Sep 17 00:00:00 2001 +From: Wesley Chalmers +Date: Wed, 21 Jun 2023 19:13:26 -0400 +Subject: [PATCH] drm/amd/display: Fix a bug when searching for insert_above_mpcc +Git-commit: 3d028d5d60d516c536de1ddd3ebf3d55f3f8983b +Patch-mainline: v6.6-rc1 +References: git-fixes + +[WHY] +Currently, when insert_plane is called with insert_above_mpcc +parameter that is equal to tree->opp_list, the function returns NULL. + +[HOW] +Instead, the function should insert the plane at the top of the tree. + +Cc: Mario Limonciello +Cc: Alex Deucher +Cc: stable@vger.kernel.org +Reviewed-by: Jun Lei +Acked-by: Tom Chung +Signed-off-by: Wesley Chalmers +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c +index 8e9384094f6d..f2f55565e98a 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c +@@ -212,8 +212,9 @@ struct mpcc *mpc1_insert_plane( + /* check insert_above_mpcc exist in tree->opp_list */ + struct mpcc *temp_mpcc = tree->opp_list; + +- while (temp_mpcc && temp_mpcc->mpcc_bot != insert_above_mpcc) +- temp_mpcc = temp_mpcc->mpcc_bot; ++ if (temp_mpcc != insert_above_mpcc) ++ while (temp_mpcc && temp_mpcc->mpcc_bot != insert_above_mpcc) ++ temp_mpcc = temp_mpcc->mpcc_bot; + if (temp_mpcc == NULL) + return NULL; + } +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Fix-possible-underflow-for-displays--de23118.patch b/patches.suse/drm-amd-display-Fix-possible-underflow-for-displays--de23118.patch new file mode 100644 index 0000000..81f51b3 --- /dev/null +++ b/patches.suse/drm-amd-display-Fix-possible-underflow-for-displays--de23118.patch @@ -0,0 +1,77 @@ +From de231189e7bf1a38c0f889ec5f8911af473aa792 Mon Sep 17 00:00:00 2001 +From: Daniel Miess +Date: Thu, 11 May 2023 10:51:27 -0400 +Subject: [PATCH] drm/amd/display: Fix possible underflow for displays with large vblank +Git-commit: de231189e7bf1a38c0f889ec5f8911af473aa792 +Patch-mainline: v6.5-rc1 +References: git-fixes + +[Why] +Underflow observed when using a display with a large vblank region +and low refresh rate + +[How] +Simplify calculation of vblank_nom + +Increase value for VBlankNomDefaultUS to 800us + +Fixed a null pointer from previous commit of this change + +Reviewed-by: Nicholas Kazlauskas +Acked-by: Tom Chung +Signed-off-by: Daniel Miess +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + .../amd/display/dc/dml/dcn314/dcn314_fpu.c | 19 +++++++------------ + 1 file changed, 7 insertions(+), 12 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c +index 1d00eb9e73c6..554152371eb5 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c +@@ -33,7 +33,7 @@ + #include "dml/display_mode_vba.h" + + struct _vcs_dpi_ip_params_st dcn3_14_ip = { +- .VBlankNomDefaultUS = 668, ++ .VBlankNomDefaultUS = 800, + .gpuvm_enable = 1, + .gpuvm_max_page_table_levels = 1, + .hostvm_enable = 1, +@@ -286,7 +286,7 @@ int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *c + struct resource_context *res_ctx = &context->res_ctx; + struct pipe_ctx *pipe; + bool upscaled = false; +- bool isFreesyncVideo = false; ++ const unsigned int max_allowed_vblank_nom = 1023; + + dc_assert_fp_enabled(); + +@@ -300,16 +300,11 @@ int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *c + pipe = &res_ctx->pipe_ctx[i]; + timing = &pipe->stream->timing; + +- isFreesyncVideo = pipe->stream->adjust.v_total_max == pipe->stream->adjust.v_total_min; +- isFreesyncVideo = isFreesyncVideo && pipe->stream->adjust.v_total_min > timing->v_total; +- +- if (!isFreesyncVideo) { +- pipes[pipe_cnt].pipe.dest.vblank_nom = +- dcn3_14_ip.VBlankNomDefaultUS / (timing->h_total / (timing->pix_clk_100hz / 10000.0)); +- } else { +- pipes[pipe_cnt].pipe.dest.vtotal = pipe->stream->adjust.v_total_min; +- pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; +- } ++ pipes[pipe_cnt].pipe.dest.vtotal = pipe->stream->adjust.v_total_min; ++ pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; ++ pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, dcn3_14_ip.VBlankNomDefaultUS); ++ pipes[pipe_cnt].pipe.dest.vblank_nom = max(pipes[pipe_cnt].pipe.dest.vblank_nom, timing->v_sync_width); ++ pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, max_allowed_vblank_nom); + + if (pipe->plane_state && + (pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height || +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Fix-possible-underflow-for-displays-.patch b/patches.suse/drm-amd-display-Fix-possible-underflow-for-displays-.patch new file mode 100644 index 0000000..c8e2ada --- /dev/null +++ b/patches.suse/drm-amd-display-Fix-possible-underflow-for-displays-.patch @@ -0,0 +1,75 @@ +From 1a4bcdbea4319efeb26cc4b05be859a7867e02dc Mon Sep 17 00:00:00 2001 +From: Daniel Miess +Date: Tue, 25 Apr 2023 14:29:48 -0400 +Subject: [PATCH] drm/amd/display: Fix possible underflow for displays with large vblank +Git-commit: 1a4bcdbea4319efeb26cc4b05be859a7867e02dc +Patch-mainline: v6.5-rc1 +References: git-fixes + +[Why] +Underflow observed when using a display with a large vblank region +and low refresh rate + +[How] +Simplify calculation of vblank_nom + +Increase value for VBlankNomDefaultUS to 800us + +Reviewed-by: Jun Lei +Acked-by: Aurabindo Pillai +Signed-off-by: Daniel Miess +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + .../amd/display/dc/dml/dcn314/dcn314_fpu.c | 19 +++++++------------ + 1 file changed, 7 insertions(+), 12 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c +index 1d00eb9e73c6..554152371eb5 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c +@@ -33,7 +33,7 @@ + #include "dml/display_mode_vba.h" + + struct _vcs_dpi_ip_params_st dcn3_14_ip = { +- .VBlankNomDefaultUS = 668, ++ .VBlankNomDefaultUS = 800, + .gpuvm_enable = 1, + .gpuvm_max_page_table_levels = 1, + .hostvm_enable = 1, +@@ -286,7 +286,7 @@ int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *c + struct resource_context *res_ctx = &context->res_ctx; + struct pipe_ctx *pipe; + bool upscaled = false; +- bool isFreesyncVideo = false; ++ const unsigned int max_allowed_vblank_nom = 1023; + + dc_assert_fp_enabled(); + +@@ -300,16 +300,11 @@ int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *c + pipe = &res_ctx->pipe_ctx[i]; + timing = &pipe->stream->timing; + +- isFreesyncVideo = pipe->stream->adjust.v_total_max == pipe->stream->adjust.v_total_min; +- isFreesyncVideo = isFreesyncVideo && pipe->stream->adjust.v_total_min > timing->v_total; +- +- if (!isFreesyncVideo) { +- pipes[pipe_cnt].pipe.dest.vblank_nom = +- dcn3_14_ip.VBlankNomDefaultUS / (timing->h_total / (timing->pix_clk_100hz / 10000.0)); +- } else { +- pipes[pipe_cnt].pipe.dest.vtotal = pipe->stream->adjust.v_total_min; +- pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; +- } ++ pipes[pipe_cnt].pipe.dest.vtotal = pipe->stream->adjust.v_total_min; ++ pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; ++ pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, dcn3_14_ip.VBlankNomDefaultUS); ++ pipes[pipe_cnt].pipe.dest.vblank_nom = max(pipes[pipe_cnt].pipe.dest.vblank_nom, timing->v_sync_width); ++ pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, max_allowed_vblank_nom); + + if (pipe->plane_state && + (pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height || +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Fix-the-delta-clamping-for-shaper-LU.patch b/patches.suse/drm-amd-display-Fix-the-delta-clamping-for-shaper-LU.patch new file mode 100644 index 0000000..fa02a45 --- /dev/null +++ b/patches.suse/drm-amd-display-Fix-the-delta-clamping-for-shaper-LU.patch @@ -0,0 +1,187 @@ +From 27fc10d1095f7a7de7c917638d7134033a190dd8 Mon Sep 17 00:00:00 2001 +From: Harry Wentland +Date: Thu, 6 Apr 2023 18:06:27 -0400 +Subject: [PATCH] drm/amd/display: Fix the delta clamping for shaper LUT +Git-commit: 27fc10d1095f7a7de7c917638d7134033a190dd8 +Patch-mainline: v6.5-rc1 +References: git-fixes + +The shaper LUT requires a 10-bit value of the delta between segments. We +were using dc_fixpt_clamp_u0d10() to do that but it doesn't do what we +want it to do. It will preserve 10-bit precision after the decimal +point, but that's not quite what we want. We want 14-bit precision and +discard the 4 most-significant bytes. + +To do that we'll do dc_fixpt_clamp_u0d14() & 0x3ff instead. + +Tested-by: Daniel Wheeler +Reviewed-by: Krunoslav Kovac +Acked-by: Rodrigo Siqueira +Signed-off-by: Harry Wentland +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + .../amd/display/dc/dcn10/dcn10_cm_common.c | 19 +++++++++++++++---- + .../amd/display/dc/dcn10/dcn10_cm_common.h | 1 + + .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +- + .../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 6 +++--- + .../drm/amd/display/dc/dcn30/dcn30_dwb_cm.c | 2 +- + .../drm/amd/display/dc/dcn30/dcn30_hwseq.c | 2 +- + .../drm/amd/display/dc/dcn32/dcn32_hwseq.c | 6 +++--- + 7 files changed, 25 insertions(+), 13 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c +index 7a00fe525dfb..3538973bd0c6 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c +@@ -308,7 +308,10 @@ bool cm_helper_convert_to_custom_float( + #define NUMBER_REGIONS 32 + #define NUMBER_SW_SEGMENTS 16 + +-bool cm_helper_translate_curve_to_hw_format( ++#define DC_LOGGER \ ++ ctx->logger ++ ++bool cm_helper_translate_curve_to_hw_format(struct dc_context *ctx, + const struct dc_transfer_func *output_tf, + struct pwl_params *lut_params, bool fixpoint) + { +@@ -482,10 +485,18 @@ bool cm_helper_translate_curve_to_hw_format( + rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green); + rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue); + ++ + if (fixpoint == true) { +- rgb->delta_red_reg = dc_fixpt_clamp_u0d10(rgb->delta_red); +- rgb->delta_green_reg = dc_fixpt_clamp_u0d10(rgb->delta_green); +- rgb->delta_blue_reg = dc_fixpt_clamp_u0d10(rgb->delta_blue); ++ uint32_t red_clamp = dc_fixpt_clamp_u0d14(rgb->delta_red); ++ uint32_t green_clamp = dc_fixpt_clamp_u0d14(rgb->delta_green); ++ uint32_t blue_clamp = dc_fixpt_clamp_u0d14(rgb->delta_blue); ++ ++ if (red_clamp >> 10 || green_clamp >> 10 || blue_clamp >> 10) ++ DC_LOG_WARNING("Losing delta precision while programming shaper LUT."); ++ ++ rgb->delta_red_reg = red_clamp & 0x3ff; ++ rgb->delta_green_reg = green_clamp & 0x3ff; ++ rgb->delta_blue_reg = blue_clamp & 0x3ff; + rgb->red_reg = dc_fixpt_clamp_u0d14(rgb->red); + rgb->green_reg = dc_fixpt_clamp_u0d14(rgb->green); + rgb->blue_reg = dc_fixpt_clamp_u0d14(rgb->blue); +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h +index 3b8cd7410498..0a68b63d6126 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h +@@ -106,6 +106,7 @@ bool cm_helper_convert_to_custom_float( + bool fixpoint); + + bool cm_helper_translate_curve_to_hw_format( ++ struct dc_context *ctx, + const struct dc_transfer_func *output_tf, + struct pwl_params *lut_params, bool fixpoint); + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index 20a1582be0b1..a50309039d08 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -1843,7 +1843,7 @@ bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, + /* dcn10_translate_regamma_to_hw_format takes 750us, only do it when full + * update. + */ +- else if (cm_helper_translate_curve_to_hw_format( ++ else if (cm_helper_translate_curve_to_hw_format(dc->ctx, + stream->out_transfer_func, + &dpp->regamma_params, false)) { + dpp->funcs->dpp_program_regamma_pwl( +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +index 4c8aa3dfb959..4492bc2392b6 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +@@ -867,7 +867,7 @@ bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, + params = &stream->out_transfer_func->pwl; + else if (pipe_ctx->stream->out_transfer_func->type == + TF_TYPE_DISTRIBUTED_POINTS && +- cm_helper_translate_curve_to_hw_format( ++ cm_helper_translate_curve_to_hw_format(dc->ctx, + stream->out_transfer_func, + &mpc->blender_params, false)) + params = &mpc->blender_params; +@@ -896,7 +896,7 @@ bool dcn20_set_blend_lut( + if (plane_state->blend_tf->type == TF_TYPE_HWPWL) + blend_lut = &plane_state->blend_tf->pwl; + else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { +- cm_helper_translate_curve_to_hw_format( ++ cm_helper_translate_curve_to_hw_format(plane_state->ctx, + plane_state->blend_tf, + &dpp_base->regamma_params, false); + blend_lut = &dpp_base->regamma_params; +@@ -918,7 +918,7 @@ bool dcn20_set_shaper_3dlut( + if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL) + shaper_lut = &plane_state->in_shaper_func->pwl; + else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) { +- cm_helper_translate_curve_to_hw_format( ++ cm_helper_translate_curve_to_hw_format(plane_state->ctx, + plane_state->in_shaper_func, + &dpp_base->shaper_params, true); + shaper_lut = &dpp_base->shaper_params; +diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb_cm.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb_cm.c +index 6a3d3a0ec0a3..701c7d8bc038 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb_cm.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb_cm.c +@@ -280,7 +280,7 @@ bool dwb3_ogam_set_input_transfer_func( + dwb_ogam_lut = kzalloc(sizeof(*dwb_ogam_lut), GFP_KERNEL); + + if (dwb_ogam_lut) { +- cm_helper_translate_curve_to_hw_format( ++ cm_helper_translate_curve_to_hw_format(dwbc->ctx, + in_transfer_func_dwb_ogam, + dwb_ogam_lut, false); + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c +index b9753867d97b..bf8864bc8a99 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c +@@ -106,7 +106,7 @@ static bool dcn30_set_mpc_shaper_3dlut(struct pipe_ctx *pipe_ctx, + if (stream->func_shaper->type == TF_TYPE_HWPWL) { + shaper_lut = &stream->func_shaper->pwl; + } else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { +- cm_helper_translate_curve_to_hw_format(stream->func_shaper, ++ cm_helper_translate_curve_to_hw_format(stream->ctx, stream->func_shaper, + &dpp_base->shaper_params, true); + shaper_lut = &dpp_base->shaper_params; + } +diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c +index e5bd76c6b1d3..526e89ef9cdc 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c +@@ -448,7 +448,7 @@ bool dcn32_set_mpc_shaper_3dlut( + if (stream->func_shaper->type == TF_TYPE_HWPWL) + shaper_lut = &stream->func_shaper->pwl; + else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { +- cm_helper_translate_curve_to_hw_format( ++ cm_helper_translate_curve_to_hw_format(stream->ctx, + stream->func_shaper, + &dpp_base->shaper_params, true); + shaper_lut = &dpp_base->shaper_params; +@@ -484,7 +484,7 @@ bool dcn32_set_mcm_luts( + if (plane_state->blend_tf->type == TF_TYPE_HWPWL) + lut_params = &plane_state->blend_tf->pwl; + else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { +- cm_helper_translate_curve_to_hw_format( ++ cm_helper_translate_curve_to_hw_format(plane_state->ctx, + plane_state->blend_tf, + &dpp_base->regamma_params, false); + lut_params = &dpp_base->regamma_params; +@@ -499,7 +499,7 @@ bool dcn32_set_mcm_luts( + else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) { + // TODO: dpp_base replace + ASSERT(false); +- cm_helper_translate_curve_to_hw_format( ++ cm_helper_translate_curve_to_hw_format(plane_state->ctx, + plane_state->in_shaper_func, + &dpp_base->shaper_params, true); + lut_params = &dpp_base->shaper_params; +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Fix-underflow-issue-on-175hz-timing.patch b/patches.suse/drm-amd-display-Fix-underflow-issue-on-175hz-timing.patch new file mode 100644 index 0000000..1aa8c0c --- /dev/null +++ b/patches.suse/drm-amd-display-Fix-underflow-issue-on-175hz-timing.patch @@ -0,0 +1,66 @@ +From 735688eb905db529efea0c78466fccc1461c3fde Mon Sep 17 00:00:00 2001 +From: Leo Ma +Date: Thu, 6 Jul 2023 16:17:03 -0400 +Subject: [PATCH] drm/amd/display: Fix underflow issue on 175hz timing +Git-commit: 735688eb905db529efea0c78466fccc1461c3fde +Patch-mainline: v6.6-rc1 +References: git-fixes + +[Why] +Screen underflows happen on 175hz timing for 3 plane overlay case. + +[How] +Based on dst y prefetch value clamp to equ or oto for bandwidth +calculation. + +Reviewed-by: Dillon Varone +Acked-by: Alex Hung +Signed-off-by: Leo Ma +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + .../amd/display/dc/dml/dcn32/display_mode_vba_util_32.c | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c +index 890797ecf0f9..ecea008f19d3 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c +@@ -3459,6 +3459,7 @@ bool dml32_CalculatePrefetchSchedule( + double TimeForFetchingMetaPTE = 0; + double TimeForFetchingRowInVBlank = 0; + double LinesToRequestPrefetchPixelData = 0; ++ double LinesForPrefetchBandwidth = 0; + unsigned int HostVMDynamicLevelsTrips; + double trip_to_mem; + double Tvm_trips; +@@ -3888,11 +3889,15 @@ bool dml32_CalculatePrefetchSchedule( + TimeForFetchingMetaPTE = Tvm_oto; + TimeForFetchingRowInVBlank = Tr0_oto; + *PrefetchBandwidth = prefetch_bw_oto; ++ /* Clamp to oto for bandwidth calculation */ ++ LinesForPrefetchBandwidth = dst_y_prefetch_oto; + } else { + *DestinationLinesForPrefetch = dst_y_prefetch_equ; + TimeForFetchingMetaPTE = Tvm_equ; + TimeForFetchingRowInVBlank = Tr0_equ; + *PrefetchBandwidth = prefetch_bw_equ; ++ /* Clamp to equ for bandwidth calculation */ ++ LinesForPrefetchBandwidth = dst_y_prefetch_equ; + } + + *DestinationLinesToRequestVMInVBlank = dml_ceil(4.0 * TimeForFetchingMetaPTE / LineTime, 1.0) / 4.0; +@@ -3900,7 +3905,7 @@ bool dml32_CalculatePrefetchSchedule( + *DestinationLinesToRequestRowInVBlank = + dml_ceil(4.0 * TimeForFetchingRowInVBlank / LineTime, 1.0) / 4.0; + +- LinesToRequestPrefetchPixelData = *DestinationLinesForPrefetch - ++ LinesToRequestPrefetchPixelData = LinesForPrefetchBandwidth - + *DestinationLinesToRequestVMInVBlank - 2 * *DestinationLinesToRequestRowInVBlank; + + #ifdef __DML_VBA_DEBUG__ +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-For-prefetch-mode-0-extend-prefetch-.patch b/patches.suse/drm-amd-display-For-prefetch-mode-0-extend-prefetch-.patch new file mode 100644 index 0000000..39ab70e --- /dev/null +++ b/patches.suse/drm-amd-display-For-prefetch-mode-0-extend-prefetch-.patch @@ -0,0 +1,124 @@ +From dd4e4bb28843393065eed279e869fac248d03f0f Mon Sep 17 00:00:00 2001 +From: Alvin Lee +Date: Wed, 6 Dec 2023 14:52:31 -0500 +Subject: [PATCH] drm/amd/display: For prefetch mode > 0, extend prefetch if possible +Git-commit: dd4e4bb28843393065eed279e869fac248d03f0f +Patch-mainline: v6.8-rc1 +References: git-fixes + +[Description] +For mode programming we want to extend the prefetch as much as possible +(up to oto, or as long as we can for equ) if we're not already applying +the 60us prefetch requirement. This is to avoid intermittent underflow +issues during prefetch. + +The prefetch extension is applied under the following scenarios: +1. We're in prefetch mode 1 (i.e. we don't support MCLK switch in blank) +2. We're using subvp or drr methods of p-state switch, in which case we + we don't care if prefetch takes up more of the blanking time + +Mode programming typically chooses the smallest prefetch time possible +(i.e. highest bandwidth during prefetch) presumably to create margin between +p-states / c-states that happen in vblank and prefetch. Therefore we only +apply this prefetch extension when p-state in vblank is not required (UCLK +p-states take up the most vblank time). + +Reviewed-by: Jun Lei +Acked-by: Aurabindo Pillai +Signed-off-by: Alvin Lee +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + .../dc/dml/dcn32/display_mode_vba_32.c | 3 ++ + .../dc/dml/dcn32/display_mode_vba_util_32.c | 33 +++++++++++++++---- + .../dc/dml/dcn32/display_mode_vba_util_32.h | 1 + + 3 files changed, 31 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c +index cbdfb762c10c..6c84b0fa40f4 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c +@@ -813,6 +813,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman + (v->DRAMSpeedPerState[mode_lib->vba.VoltageLevel] <= MEM_STROBE_FREQ_MHZ || + v->DCFCLKPerState[mode_lib->vba.VoltageLevel] <= DCFCLK_FREQ_EXTRA_PREFETCH_REQ_MHZ) ? + mode_lib->vba.ip.min_prefetch_in_strobe_us : 0, ++ mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] > 0 || mode_lib->vba.DRAMClockChangeRequirementFinal == false, ++ + /* Output */ + &v->DSTXAfterScaler[k], + &v->DSTYAfterScaler[k], +@@ -3317,6 +3319,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l + v->SwathHeightCThisState[k], v->TWait, + (v->DRAMSpeedPerState[i] <= MEM_STROBE_FREQ_MHZ || v->DCFCLKState[i][j] <= DCFCLK_FREQ_EXTRA_PREFETCH_REQ_MHZ) ? + mode_lib->vba.ip.min_prefetch_in_strobe_us : 0, ++ mode_lib->vba.PrefetchModePerState[i][j] > 0 || mode_lib->vba.DRAMClockChangeRequirementFinal == false, + + /* Output */ + &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTXAfterScaler[k], +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c +index d940dfa5ae43..80fccd4999a5 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c +@@ -3423,6 +3423,7 @@ bool dml32_CalculatePrefetchSchedule( + unsigned int SwathHeightC, + double TWait, + double TPreReq, ++ bool ExtendPrefetchIfPossible, + /* Output */ + double *DSTXAfterScaler, + double *DSTYAfterScaler, +@@ -3892,12 +3893,32 @@ bool dml32_CalculatePrefetchSchedule( + /* Clamp to oto for bandwidth calculation */ + LinesForPrefetchBandwidth = dst_y_prefetch_oto; + } else { +- *DestinationLinesForPrefetch = dst_y_prefetch_equ; +- TimeForFetchingMetaPTE = Tvm_equ; +- TimeForFetchingRowInVBlank = Tr0_equ; +- *PrefetchBandwidth = prefetch_bw_equ; +- /* Clamp to equ for bandwidth calculation */ +- LinesForPrefetchBandwidth = dst_y_prefetch_equ; ++ /* For mode programming we want to extend the prefetch as much as possible ++ * (up to oto, or as long as we can for equ) if we're not already applying ++ * the 60us prefetch requirement. This is to avoid intermittent underflow ++ * issues during prefetch. ++ * ++ * The prefetch extension is applied under the following scenarios: ++ * 1. We're in prefetch mode > 0 (i.e. we don't support MCLK switch in blank) ++ * 2. We're using subvp or drr methods of p-state switch, in which case we ++ * we don't care if prefetch takes up more of the blanking time ++ * ++ * Mode programming typically chooses the smallest prefetch time possible ++ * (i.e. highest bandwidth during prefetch) presumably to create margin between ++ * p-states / c-states that happen in vblank and prefetch. Therefore we only ++ * apply this prefetch extension when p-state in vblank is not required (UCLK ++ * p-states take up the most vblank time). ++ */ ++ if (ExtendPrefetchIfPossible && TPreReq == 0 && VStartup < MaxVStartup) { ++ MyError = true; ++ } else { ++ *DestinationLinesForPrefetch = dst_y_prefetch_equ; ++ TimeForFetchingMetaPTE = Tvm_equ; ++ TimeForFetchingRowInVBlank = Tr0_equ; ++ *PrefetchBandwidth = prefetch_bw_equ; ++ /* Clamp to equ for bandwidth calculation */ ++ LinesForPrefetchBandwidth = dst_y_prefetch_equ; ++ } + } + + *DestinationLinesToRequestVMInVBlank = dml_ceil(4.0 * TimeForFetchingMetaPTE / LineTime, 1.0) / 4.0; +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h +index 592d174df6c6..5d34735df83d 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h +@@ -747,6 +747,7 @@ bool dml32_CalculatePrefetchSchedule( + unsigned int SwathHeightC, + double TWait, + double TPreReq, ++ bool ExtendPrefetchIfPossible, + /* Output */ + double *DSTXAfterScaler, + double *DSTYAfterScaler, +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Guard-DCN31-PHYD32CLK-logic-against-.patch b/patches.suse/drm-amd-display-Guard-DCN31-PHYD32CLK-logic-against-.patch new file mode 100644 index 0000000..9864dbc --- /dev/null +++ b/patches.suse/drm-amd-display-Guard-DCN31-PHYD32CLK-logic-against-.patch @@ -0,0 +1,43 @@ +From 25b054c3c89cb6a7106a7982f0f70e83d0797dab Mon Sep 17 00:00:00 2001 +From: George Shen +Date: Tue, 11 Jul 2023 13:22:36 -0400 +Subject: [PATCH] drm/amd/display: Guard DCN31 PHYD32CLK logic against chip family +Git-commit: 25b054c3c89cb6a7106a7982f0f70e83d0797dab +Patch-mainline: v6.5-rc4 +References: git-fixes + +[Why] +Current yellow carp B0 PHYD32CLK logic is incorrectly applied to other +ASICs. + +[How] +Add guard to check chip family is yellow carp before applying logic. + +Reviewed-by: Hansen Dsouza +Acked-by: Alex Hung +Signed-off-by: George Shen +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c +index 65c1d754e2d6..01cc679ae418 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c +@@ -84,7 +84,8 @@ static enum phyd32clk_clock_source get_phy_mux_symclk( + struct dcn_dccg *dccg_dcn, + enum phyd32clk_clock_source src) + { +- if (dccg_dcn->base.ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) { ++ if (dccg_dcn->base.ctx->asic_id.chip_family == FAMILY_YELLOW_CARP && ++ dccg_dcn->base.ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) { + if (src == PHYD32CLKC) + src = PHYD32CLKF; + if (src == PHYD32CLKD) +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Guard-against-invalid-RPTR-WPTR-bein.patch b/patches.suse/drm-amd-display-Guard-against-invalid-RPTR-WPTR-bein.patch new file mode 100644 index 0000000..1d0239c --- /dev/null +++ b/patches.suse/drm-amd-display-Guard-against-invalid-RPTR-WPTR-bein.patch @@ -0,0 +1,68 @@ +From 1ffa8602e39b89469dc703ebab7a7e44c33da0f7 Mon Sep 17 00:00:00 2001 +From: Nicholas Kazlauskas +Date: Wed, 13 Sep 2023 16:18:44 -0400 +Subject: [PATCH] drm/amd/display: Guard against invalid RPTR/WPTR being set +Git-commit: 1ffa8602e39b89469dc703ebab7a7e44c33da0f7 +Patch-mainline: v6.7-rc2 +References: git-fixes + +[WHY] +HW can return invalid values on register read, guard against these being +set and causing us to access memory out of range and page fault. + +[HOW] +Guard at sync_inbox1 and guard at pushing commands. + +Cc: Mario Limonciello +Cc: Alex Deucher +Cc: stable@vger.kernel.org +Reviewed-by: Hansen Dsouza +Acked-by: Alex Hung +Signed-off-by: Nicholas Kazlauskas +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + .../gpu/drm/amd/display/dmub/src/dmub_srv.c | 18 +++++++++++++++--- + 1 file changed, 15 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +index e43e8d4bfe37..5d36f3e5dc2b 100644 +--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c ++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +@@ -707,9 +707,16 @@ enum dmub_status dmub_srv_sync_inbox1(struct dmub_srv *dmub) + return DMUB_STATUS_INVALID; + + if (dmub->hw_funcs.get_inbox1_rptr && dmub->hw_funcs.get_inbox1_wptr) { +- dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); +- dmub->inbox1_rb.wrpt = dmub->hw_funcs.get_inbox1_wptr(dmub); +- dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt; ++ uint32_t rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); ++ uint32_t wptr = dmub->hw_funcs.get_inbox1_wptr(dmub); ++ ++ if (rptr > dmub->inbox1_rb.capacity || wptr > dmub->inbox1_rb.capacity) { ++ return DMUB_STATUS_HW_FAILURE; ++ } else { ++ dmub->inbox1_rb.rptr = rptr; ++ dmub->inbox1_rb.wrpt = wptr; ++ dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt; ++ } + } + + return DMUB_STATUS_OK; +@@ -743,6 +750,11 @@ enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub, + if (!dmub->hw_init) + return DMUB_STATUS_INVALID; + ++ if (dmub->inbox1_rb.rptr > dmub->inbox1_rb.capacity || ++ dmub->inbox1_rb.wrpt > dmub->inbox1_rb.capacity) { ++ return DMUB_STATUS_HW_FAILURE; ++ } ++ + if (dmub_rb_push_front(&dmub->inbox1_rb, cmd)) + return DMUB_STATUS_OK; + +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Handle-seamless-boot-stream.patch b/patches.suse/drm-amd-display-Handle-seamless-boot-stream.patch new file mode 100644 index 0000000..91afd12 --- /dev/null +++ b/patches.suse/drm-amd-display-Handle-seamless-boot-stream.patch @@ -0,0 +1,54 @@ +From 170390e587a69b2a24abac39eb3ae6ec28a4d7f2 Mon Sep 17 00:00:00 2001 +From: Rodrigo Siqueira +Date: Tue, 18 Oct 2022 08:28:22 -0400 +Subject: [PATCH] drm/amd/display: Handle seamless boot stream +Git-commit: 170390e587a69b2a24abac39eb3ae6ec28a4d7f2 +Patch-mainline: v6.2-rc1 +References: git-fixes + +A seamless boot stream has hardware resources assigned to it, and adding +a new stream means rebuilding the current assignment. It is desirable to +avoid this situation since it may cause light-up issues on the VGA +monitor on USB-C. This commit swaps the seamless boot stream to pipe 0 +(if necessary) to ensure that the pipe context matches. + +Reviewed-by: Harry Wentland +Signed-off-by: Rodrigo Siqueira +Co-developed-by: Aurabindo Pillai +Signed-off-by: Aurabindo Pillai +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +index e001b138b2ac..ba2d4347f722 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +@@ -2765,6 +2765,21 @@ enum dc_status dc_validate_with_context(struct dc *dc, + goto fail; + } + ++ /* Swap seamless boot stream to pipe 0 (if needed) to ensure pipe_ctx ++ * matches. This may change in the future if seamless_boot_stream can be ++ * multiple. ++ */ ++ for (i = 0; i < add_streams_count; i++) { ++ mark_seamless_boot_stream(dc, add_streams[i]); ++ if (add_streams[i]->apply_seamless_boot_optimization && i != 0) { ++ struct dc_stream_state *temp = add_streams[0]; ++ ++ add_streams[0] = add_streams[i]; ++ add_streams[i] = temp; ++ break; ++ } ++ } ++ + /* Add new streams and then add all planes for the new stream */ + for (i = 0; i < add_streams_count; i++) { + calculate_phy_pix_clks(add_streams[i]); +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Handle-virtual-hardware-detect.patch b/patches.suse/drm-amd-display-Handle-virtual-hardware-detect.patch new file mode 100644 index 0000000..4fc2117 --- /dev/null +++ b/patches.suse/drm-amd-display-Handle-virtual-hardware-detect.patch @@ -0,0 +1,39 @@ +From 987b96eb860036ab79051fb271f7fbdc01c9daf5 Mon Sep 17 00:00:00 2001 +From: Rodrigo Siqueira +Date: Tue, 18 Oct 2022 08:28:20 -0400 +Subject: [PATCH] drm/amd/display: Handle virtual hardware detect +Git-commit: 987b96eb860036ab79051fb271f7fbdc01c9daf5 +Patch-mainline: v6.2-rc1 +References: git-fixes + +If virtual hardware is detected, there is no reason to run the full +dc_commit_streams process, and DC can return true immediately. + +Reviewed-by: Harry Wentland +Signed-off-by: Rodrigo Siqueira +Co-developed-by: Aurabindo Pillai +Signed-off-by: Aurabindo Pillai +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dc/core/dc.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index b904b03cf94e..61b574b9e736 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -1912,6 +1912,9 @@ enum dc_status dc_commit_streams(struct dc *dc, + enum dc_status res = DC_OK; + struct dc_validation_set set[MAX_STREAMS] = {0}; + ++ if (dc->ctx->dce_environment == DCE_ENV_VIRTUAL_HW) ++ return res; ++ + if (!streams_changed(dc, streams, stream_count)) + return res; + +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Include-surface-of-unaffected-stream.patch b/patches.suse/drm-amd-display-Include-surface-of-unaffected-stream.patch new file mode 100644 index 0000000..22abffb --- /dev/null +++ b/patches.suse/drm-amd-display-Include-surface-of-unaffected-stream.patch @@ -0,0 +1,111 @@ +From f6ae69f49fcf697b6ffa93d58eb3746897f61cf8 Mon Sep 17 00:00:00 2001 +From: Rodrigo Siqueira +Date: Tue, 18 Oct 2022 08:28:19 -0400 +Subject: [PATCH] drm/amd/display: Include surface of unaffected streams +Git-commit: f6ae69f49fcf697b6ffa93d58eb3746897f61cf8 +Patch-mainline: v6.2-rc1 +References: git-fixes + +The commit stream function does not include surfaces of unaffected +streams, which may lead to some blank screens during mode change in some +edge cases. This commit adds surfaces of unaffected streams followed by +kernel-doc for documenting some of the fields that participate in this +change. + +V2: squash in kerneldoc warning fix (Alex) + +Reviewed-by: Harry Wentland +Signed-off-by: Rodrigo Siqueira +Co-developed-by: Aurabindo Pillai +Signed-off-by: Aurabindo Pillai +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dc/core/dc.c | 12 +++++++++++- + drivers/gpu/drm/amd/display/dc/dc.h | 15 +++++++++++++-- + drivers/gpu/drm/amd/display/dc/dc_stream.h | 4 ++++ + 3 files changed, 28 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index af81c2835738..b904b03cf94e 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -1907,9 +1907,10 @@ enum dc_status dc_commit_streams(struct dc *dc, + struct dc_stream_state *streams[], + uint8_t stream_count) + { +- int i; ++ int i, j; + struct dc_state *context; + enum dc_status res = DC_OK; ++ struct dc_validation_set set[MAX_STREAMS] = {0}; + + if (!streams_changed(dc, streams, stream_count)) + return res; +@@ -1918,8 +1919,17 @@ enum dc_status dc_commit_streams(struct dc *dc, + + for (i = 0; i < stream_count; i++) { + struct dc_stream_state *stream = streams[i]; ++ struct dc_stream_status *status = dc_stream_get_status(stream); + + dc_stream_log(dc, stream); ++ ++ set[i].stream = stream; ++ ++ if (status) { ++ set[i].plane_count = status->plane_count; ++ for (j = 0; j < status->plane_count; j++) ++ set[i].plane_states[j] = status->plane_states[j]; ++ } + } + + context = dc_create_state(dc); +diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h +index 6adecb62e534..836cdf5d4114 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc.h ++++ b/drivers/gpu/drm/amd/display/dc/dc.h +@@ -1269,12 +1269,23 @@ void dc_post_update_surfaces_to_stream( + + #include "dc_stream.h" + +-/* +- * Structure to store surface/stream associations for validation ++/** ++ * struct dc_validation_set - Struct to store surface/stream associations for validation + */ + struct dc_validation_set { ++ /** ++ * @stream: Stream state properties ++ */ + struct dc_stream_state *stream; ++ ++ /** ++ * @plane_state: Surface state ++ */ + struct dc_plane_state *plane_states[MAX_SURFACES]; ++ ++ /** ++ * @plane_count: Total of active planes ++ */ + uint8_t plane_count; + }; + +diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h +index 9e6025c98db9..73dccd485895 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h ++++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h +@@ -41,6 +41,10 @@ struct timing_sync_info { + struct dc_stream_status { + int primary_otg_inst; + int stream_enc_inst; ++ ++ /** ++ * @plane_count: Total of planes attached to a single stream ++ */ + int plane_count; + int audio_inst; + struct timing_sync_info timing_sync_info; +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Include-udelay-when-waiting-for-INBO.patch b/patches.suse/drm-amd-display-Include-udelay-when-waiting-for-INBO.patch new file mode 100644 index 0000000..95bd864 --- /dev/null +++ b/patches.suse/drm-amd-display-Include-udelay-when-waiting-for-INBO.patch @@ -0,0 +1,38 @@ +From 3c9ea68cb61bd7e5bd312c06a12adada74ff5805 Mon Sep 17 00:00:00 2001 +From: Alvin Lee +Date: Mon, 6 Nov 2023 11:20:15 -0500 +Subject: [PATCH] drm/amd/display: Include udelay when waiting for INBOX0 ACK +Git-commit: 3c9ea68cb61bd7e5bd312c06a12adada74ff5805 +Patch-mainline: v6.7-rc4 +References: git-fixes + +When waiting for the ACK for INBOX0 message, +we have to ensure to include the udelay +for proper wait time + +Cc: stable@vger.kernel.org # 6.1+ +Reviewed-by: Samson Tam +Acked-by: Hamza Mahfooz +Signed-off-by: Alvin Lee +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +index 22fc4ba96def..38360adc53d9 100644 +--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c ++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +@@ -1077,6 +1077,7 @@ enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t ti + ack = dmub->hw_funcs.read_inbox0_ack_register(dmub); + if (ack) + return DMUB_STATUS_OK; ++ udelay(1); + } + return DMUB_STATUS_TIMEOUT; + } +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Increase-frame-warning-limit-with-KA.patch b/patches.suse/drm-amd-display-Increase-frame-warning-limit-with-KA.patch new file mode 100644 index 0000000..c7a211a --- /dev/null +++ b/patches.suse/drm-amd-display-Increase-frame-warning-limit-with-KA.patch @@ -0,0 +1,41 @@ +From 5b750b22530fe53bf7fd6a30baacd53ada26911b Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Thu, 30 Nov 2023 17:34:07 -0500 +Subject: [PATCH] drm/amd/display: Increase frame warning limit with KASAN or KCSAN in dml +Git-commit: 5b750b22530fe53bf7fd6a30baacd53ada26911b +Patch-mainline: v6.7-rc5 +References: git-fixes + +Does the same thing as: +commit 6740ec97bcdb ("drm/amd/display: Increase frame warning limit with KASAN or KCSAN in dml2") + +Reviewed-by: Harry Wentland +Reported-by: kernel test robot +Closes: https://lore.kernel.org/oe-kbuild-all/202311302107.hUDXVyWT-lkp@intel.com/ +Fixes: 67e38874b85b ("drm/amd/display: Increase num voltage states to 40") +Signed-off-by: Alex Deucher +Cc: Alvin Lee +Cc: Hamza Mahfooz +Cc: Samson Tam +Cc: Harry Wentland +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dc/dml/Makefile | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/gpu/drm/amd/display/dc/dml/Makefile ++++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile +@@ -51,8 +51,12 @@ endif + endif + + ifneq ($(CONFIG_FRAME_WARN),0) ++ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y) ++frame_warn_flag := -Wframe-larger-than=3072 ++else + frame_warn_flag := -Wframe-larger-than=2048 + endif ++endif + + CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags) + diff --git a/patches.suse/drm-amd-display-Keep-PHY-active-for-dp-config.patch b/patches.suse/drm-amd-display-Keep-PHY-active-for-dp-config.patch new file mode 100644 index 0000000..c0fc6a5 --- /dev/null +++ b/patches.suse/drm-amd-display-Keep-PHY-active-for-dp-config.patch @@ -0,0 +1,45 @@ +From 2b02d746c1818baf741f4eeeff9b97ab4b81e1cf Mon Sep 17 00:00:00 2001 +From: Agustin Gutierrez +Date: Tue, 21 Feb 2023 16:08:15 -0500 +Subject: [PATCH] drm/amd/display: Keep PHY active for dp config +Git-commit: 2b02d746c1818baf741f4eeeff9b97ab4b81e1cf +Patch-mainline: v6.4-rc1 +References: git-fixes + +[Why] +Current hotplug sequence causes temporary hang at the re-entry of the +optimized power state. + +[How] +Keep a PHY active when detecting DP signal + DPMS active + +Reviewed-by: Nicholas Kazlauskas +Acked-by: Qingqing Zhuo +Signed-off-by: Agustin Gutierrez +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + .../gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c +index 89df7244b272..5cb44f838bde 100644 +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c +@@ -108,6 +108,11 @@ static int dcn314_get_active_display_cnt_wa( + stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK || + stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) + tmds_present = true; ++ ++ /* Checking stream / link detection ensuring that PHY is active*/ ++ if (dc_is_dp_signal(stream->signal) && !stream->dpms_off) ++ display_count++; ++ + } + + for (i = 0; i < dc->link_count; i++) { +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Prevent-vtotal-from-being-set-to-0.patch b/patches.suse/drm-amd-display-Prevent-vtotal-from-being-set-to-0.patch new file mode 100644 index 0000000..066beaf --- /dev/null +++ b/patches.suse/drm-amd-display-Prevent-vtotal-from-being-set-to-0.patch @@ -0,0 +1,51 @@ +From 2a9482e55968ed7368afaa9c2133404069117320 Mon Sep 17 00:00:00 2001 +From: Daniel Miess +Date: Thu, 22 Jun 2023 08:11:48 -0400 +Subject: [PATCH] drm/amd/display: Prevent vtotal from being set to 0 +Git-commit: 2a9482e55968ed7368afaa9c2133404069117320 +Patch-mainline: v6.5-rc3 +References: git-fixes + +[Why] +In dcn314 DML the destination pipe vtotal was being set +to the crtc adjustment vtotal_min value even in cases +where that value is 0. + +[How] +Only set vtotal to the crtc adjustment vtotal_min value +in cases where the value is non-zero. + +Cc: Mario Limonciello +Cc: Alex Deucher +Cc: stable@vger.kernel.org +Reviewed-by: Nicholas Kazlauskas +Acked-by: Alan Liu +Signed-off-by: Daniel Miess +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c +index d9e049e7ff0a..ed8ddb75b333 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c +@@ -295,7 +295,11 @@ int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *c + pipe = &res_ctx->pipe_ctx[i]; + timing = &pipe->stream->timing; + +- pipes[pipe_cnt].pipe.dest.vtotal = pipe->stream->adjust.v_total_min; ++ if (pipe->stream->adjust.v_total_min != 0) ++ pipes[pipe_cnt].pipe.dest.vtotal = pipe->stream->adjust.v_total_min; ++ else ++ pipes[pipe_cnt].pipe.dest.vtotal = timing->v_total; ++ + pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; + pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, dcn3_14_ip.VBlankNomDefaultUS); + pipes[pipe_cnt].pipe.dest.vblank_nom = max(pipes[pipe_cnt].pipe.dest.vblank_nom, timing->v_sync_width); +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Remove-min_dst_y_next_start-check-fo.patch b/patches.suse/drm-amd-display-Remove-min_dst_y_next_start-check-fo.patch new file mode 100644 index 0000000..489370a --- /dev/null +++ b/patches.suse/drm-amd-display-Remove-min_dst_y_next_start-check-fo.patch @@ -0,0 +1,75 @@ +From 08448812acb2ab701cd5ff7e1a1dc97f7f10260c Mon Sep 17 00:00:00 2001 +From: Nicholas Kazlauskas +Date: Wed, 8 Nov 2023 10:55:53 -0500 +Subject: [PATCH] drm/amd/display: Remove min_dst_y_next_start check for Z8 +Git-commit: 08448812acb2ab701cd5ff7e1a1dc97f7f10260c +Patch-mainline: v6.7-rc4 +References: git-fixes + +[Why] +Flickering occurs on DRR supported panels when engaged in DRR due to +min_dst_y_next becoming larger than the frame size itself. + +[How] +In general, we should be able to enter Z8 when this is engaged but it +might be a net power loss even if the calculation wasn't bugged. + +Don't support enabling Z8 during the DRR region. + +Cc: stable@vger.kernel.org # 6.1+ +Reviewed-by: Syed Hassan +Acked-by: Hamza Mahfooz +Signed-off-by: Nicholas Kazlauskas +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + .../gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 15 +-------------- + 1 file changed, 1 insertion(+), 14 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +index 7fc8b18096ba..ec77b2b41ba3 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +@@ -950,10 +950,8 @@ static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struc + { + int plane_count; + int i; +- unsigned int min_dst_y_next_start_us; + + plane_count = 0; +- min_dst_y_next_start_us = 0; + for (i = 0; i < dc->res_pool->pipe_count; i++) { + if (context->res_ctx.pipe_ctx[i].plane_state) + plane_count++; +@@ -975,26 +973,15 @@ static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struc + else if (context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) { + struct dc_link *link = context->streams[0]->sink->link; + struct dc_stream_status *stream_status = &context->stream_status[0]; +- struct dc_stream_state *current_stream = context->streams[0]; + int minmum_z8_residency = dc->debug.minimum_z8_residency_time > 0 ? dc->debug.minimum_z8_residency_time : 1000; + bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency; + bool is_pwrseq0 = link->link_index == 0; +- bool isFreesyncVideo; +- +- isFreesyncVideo = current_stream->adjust.v_total_min == current_stream->adjust.v_total_max; +- isFreesyncVideo = isFreesyncVideo && current_stream->timing.v_total < current_stream->adjust.v_total_min; +- for (i = 0; i < dc->res_pool->pipe_count; i++) { +- if (context->res_ctx.pipe_ctx[i].stream == current_stream && isFreesyncVideo) { +- min_dst_y_next_start_us = context->res_ctx.pipe_ctx[i].dlg_regs.min_dst_y_next_start_us; +- break; +- } +- } + + /* Don't support multi-plane configurations */ + if (stream_status->plane_count > 1) + return DCN_ZSTATE_SUPPORT_DISALLOW; + +- if (is_pwrseq0 && (context->bw_ctx.dml.vba.StutterPeriod > 5000.0 || min_dst_y_next_start_us > 5000)) ++ if (is_pwrseq0 && context->bw_ctx.dml.vba.StutterPeriod > 5000.0) + return DCN_ZSTATE_SUPPORT_ALLOW; + else if (is_pwrseq0 && link->psr_settings.psr_version == DC_PSR_VERSION_1 && !link->panel_config.psr.disable_psr) + return allow_z8 ? DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY : DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY; +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Restore-rptr-wptr-for-DMCUB-as-worka.patch b/patches.suse/drm-amd-display-Restore-rptr-wptr-for-DMCUB-as-worka.patch new file mode 100644 index 0000000..396c808 --- /dev/null +++ b/patches.suse/drm-amd-display-Restore-rptr-wptr-for-DMCUB-as-worka.patch @@ -0,0 +1,203 @@ +From 8f3589bb6fcea397775398cba4fbcc46829a60ed Mon Sep 17 00:00:00 2001 +From: "JinZe.Xu" +Date: Mon, 10 Apr 2023 23:23:37 +0800 +Subject: [PATCH] drm/amd/display: Restore rptr/wptr for DMCUB as workaround +Git-commit: 8f3589bb6fcea397775398cba4fbcc46829a60ed +Patch-mainline: v6.5-rc1 +References: git-fixes + +[Why] +States may be desync after resume. + +[How] +Sync sw state with hw state. + +Tested-by: Daniel Wheeler +Reviewed-by: Nicholas Kazlauskas +Acked-by: Rodrigo Siqueira +Signed-off-by: JinZe.Xu +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 14 ++++++++++++++ + .../gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 5 +++++ + .../gpu/drm/amd/display/dmub/src/dmub_dcn20.h | 2 ++ + .../gpu/drm/amd/display/dmub/src/dmub_dcn31.c | 5 +++++ + .../gpu/drm/amd/display/dmub/src/dmub_dcn31.h | 2 ++ + .../gpu/drm/amd/display/dmub/src/dmub_dcn32.c | 5 +++++ + .../gpu/drm/amd/display/dmub/src/dmub_dcn32.h | 2 ++ + drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 17 +++++++++++++++++ + 8 files changed, 52 insertions(+) + +diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h +index 719bf9bb168a..d35432c21856 100644 +--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h ++++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h +@@ -340,6 +340,8 @@ struct dmub_srv_hw_funcs { + void (*setup_mailbox)(struct dmub_srv *dmub, + const struct dmub_region *inbox1); + ++ uint32_t (*get_inbox1_wptr)(struct dmub_srv *dmub); ++ + uint32_t (*get_inbox1_rptr)(struct dmub_srv *dmub); + + void (*set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset); +@@ -600,6 +602,18 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, + */ + enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub); + ++/** ++ * dmub_srv_sync_inbox1() - sync sw state with hw state ++ * @dmub: the dmub service ++ * ++ * Sync sw state with hw state when resume from S0i3 ++ * ++ * Return: ++ * DMUB_STATUS_OK - success ++ * DMUB_STATUS_INVALID - unspecified error ++ */ ++enum dmub_status dmub_srv_sync_inbox1(struct dmub_srv *dmub); ++ + /** + * dmub_srv_cmd_queue() - queues a command to the DMUB + * @dmub: the dmub service +diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c +index a6540e27044d..98dad0d47e72 100644 +--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c ++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c +@@ -282,6 +282,11 @@ void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub, + REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base); + } + ++uint32_t dmub_dcn20_get_inbox1_wptr(struct dmub_srv *dmub) ++{ ++ return REG_READ(DMCUB_INBOX1_WPTR); ++} ++ + uint32_t dmub_dcn20_get_inbox1_rptr(struct dmub_srv *dmub) + { + return REG_READ(DMCUB_INBOX1_RPTR); +diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h +index c2e5831ac52c..1df128e57ed3 100644 +--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h ++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h +@@ -202,6 +202,8 @@ void dmub_dcn20_setup_windows(struct dmub_srv *dmub, + void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub, + const struct dmub_region *inbox1); + ++uint32_t dmub_dcn20_get_inbox1_wptr(struct dmub_srv *dmub); ++ + uint32_t dmub_dcn20_get_inbox1_rptr(struct dmub_srv *dmub); + + void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset); +diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c +index c90b9ee42e12..ebf7aeec4029 100644 +--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c ++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c +@@ -242,6 +242,11 @@ void dmub_dcn31_setup_mailbox(struct dmub_srv *dmub, + REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base); + } + ++uint32_t dmub_dcn31_get_inbox1_wptr(struct dmub_srv *dmub) ++{ ++ return REG_READ(DMCUB_INBOX1_WPTR); ++} ++ + uint32_t dmub_dcn31_get_inbox1_rptr(struct dmub_srv *dmub) + { + return REG_READ(DMCUB_INBOX1_RPTR); +diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h +index f6db6f89d45d..7d5c10ee539b 100644 +--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h ++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h +@@ -204,6 +204,8 @@ void dmub_dcn31_setup_windows(struct dmub_srv *dmub, + void dmub_dcn31_setup_mailbox(struct dmub_srv *dmub, + const struct dmub_region *inbox1); + ++uint32_t dmub_dcn31_get_inbox1_wptr(struct dmub_srv *dmub); ++ + uint32_t dmub_dcn31_get_inbox1_rptr(struct dmub_srv *dmub); + + void dmub_dcn31_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset); +diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c +index a7d5607459ed..21dd6cbdb106 100644 +--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c ++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c +@@ -266,6 +266,11 @@ void dmub_dcn32_setup_mailbox(struct dmub_srv *dmub, + REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base); + } + ++uint32_t dmub_dcn32_get_inbox1_wptr(struct dmub_srv *dmub) ++{ ++ return REG_READ(DMCUB_INBOX1_WPTR); ++} ++ + uint32_t dmub_dcn32_get_inbox1_rptr(struct dmub_srv *dmub) + { + return REG_READ(DMCUB_INBOX1_RPTR); +diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h +index 7d1a6eb4d665..f15336b6e22b 100644 +--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h ++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h +@@ -206,6 +206,8 @@ void dmub_dcn32_setup_windows(struct dmub_srv *dmub, + void dmub_dcn32_setup_mailbox(struct dmub_srv *dmub, + const struct dmub_region *inbox1); + ++uint32_t dmub_dcn32_get_inbox1_wptr(struct dmub_srv *dmub); ++ + uint32_t dmub_dcn32_get_inbox1_rptr(struct dmub_srv *dmub); + + void dmub_dcn32_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset); +diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +index 67c53f7e589c..ea3bed70a229 100644 +--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c ++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +@@ -166,6 +166,7 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) + funcs->backdoor_load = dmub_dcn20_backdoor_load; + funcs->setup_windows = dmub_dcn20_setup_windows; + funcs->setup_mailbox = dmub_dcn20_setup_mailbox; ++ funcs->get_inbox1_wptr = dmub_dcn20_get_inbox1_wptr; + funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr; + funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr; + funcs->is_supported = dmub_dcn20_is_supported; +@@ -235,6 +236,7 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) + funcs->backdoor_load = dmub_dcn31_backdoor_load; + funcs->setup_windows = dmub_dcn31_setup_windows; + funcs->setup_mailbox = dmub_dcn31_setup_mailbox; ++ funcs->get_inbox1_wptr = dmub_dcn31_get_inbox1_wptr; + funcs->get_inbox1_rptr = dmub_dcn31_get_inbox1_rptr; + funcs->set_inbox1_wptr = dmub_dcn31_set_inbox1_wptr; + funcs->setup_out_mailbox = dmub_dcn31_setup_out_mailbox; +@@ -273,6 +275,7 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) + funcs->backdoor_load_zfb_mode = dmub_dcn32_backdoor_load_zfb_mode; + funcs->setup_windows = dmub_dcn32_setup_windows; + funcs->setup_mailbox = dmub_dcn32_setup_mailbox; ++ funcs->get_inbox1_wptr = dmub_dcn32_get_inbox1_wptr; + funcs->get_inbox1_rptr = dmub_dcn32_get_inbox1_rptr; + funcs->set_inbox1_wptr = dmub_dcn32_set_inbox1_wptr; + funcs->setup_out_mailbox = dmub_dcn32_setup_out_mailbox; +@@ -642,6 +645,20 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, + return DMUB_STATUS_OK; + } + ++enum dmub_status dmub_srv_sync_inbox1(struct dmub_srv *dmub) ++{ ++ if (!dmub->sw_init) ++ return DMUB_STATUS_INVALID; ++ ++ if (dmub->hw_funcs.get_inbox1_rptr && dmub->hw_funcs.get_inbox1_wptr) { ++ dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); ++ dmub->inbox1_rb.wrpt = dmub->hw_funcs.get_inbox1_wptr(dmub); ++ dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt; ++ } ++ ++ return DMUB_STATUS_OK; ++} ++ + enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub) + { + if (!dmub->sw_init) +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Revert-vblank-change-that-causes-nul.patch b/patches.suse/drm-amd-display-Revert-vblank-change-that-causes-nul.patch new file mode 100644 index 0000000..627cf8a --- /dev/null +++ b/patches.suse/drm-amd-display-Revert-vblank-change-that-causes-nul.patch @@ -0,0 +1,70 @@ +From c02b04633c4f4654331c53966cb937df1c73a9bb Mon Sep 17 00:00:00 2001 +From: Daniel Miess +Date: Thu, 11 May 2023 09:12:09 -0400 +Subject: [PATCH] drm/amd/display: Revert vblank change that causes null pointer crash +Git-commit: c02b04633c4f4654331c53966cb937df1c73a9bb +Patch-mainline: v6.5-rc1 +References: git-fixes + +Revert commit 1a4bcdbea431 ("drm/amd/display: Fix possible underflow for displays with large vblank") +Because it cause some regression + +Fixes: 1a4bcdbea431 ("drm/amd/display: Fix possible underflow for displays with large vblank") +Reviewed-by: Nicholas Kazlauskas +Acked-by: Tom Chung +Signed-off-by: Daniel Miess +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + .../amd/display/dc/dml/dcn314/dcn314_fpu.c | 19 ++++++++++++------- + 1 file changed, 12 insertions(+), 7 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c +index 554152371eb5..1d00eb9e73c6 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c +@@ -33,7 +33,7 @@ + #include "dml/display_mode_vba.h" + + struct _vcs_dpi_ip_params_st dcn3_14_ip = { +- .VBlankNomDefaultUS = 800, ++ .VBlankNomDefaultUS = 668, + .gpuvm_enable = 1, + .gpuvm_max_page_table_levels = 1, + .hostvm_enable = 1, +@@ -286,7 +286,7 @@ int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *c + struct resource_context *res_ctx = &context->res_ctx; + struct pipe_ctx *pipe; + bool upscaled = false; +- const unsigned int max_allowed_vblank_nom = 1023; ++ bool isFreesyncVideo = false; + + dc_assert_fp_enabled(); + +@@ -300,11 +300,16 @@ int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *c + pipe = &res_ctx->pipe_ctx[i]; + timing = &pipe->stream->timing; + +- pipes[pipe_cnt].pipe.dest.vtotal = pipe->stream->adjust.v_total_min; +- pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; +- pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, dcn3_14_ip.VBlankNomDefaultUS); +- pipes[pipe_cnt].pipe.dest.vblank_nom = max(pipes[pipe_cnt].pipe.dest.vblank_nom, timing->v_sync_width); +- pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, max_allowed_vblank_nom); ++ isFreesyncVideo = pipe->stream->adjust.v_total_max == pipe->stream->adjust.v_total_min; ++ isFreesyncVideo = isFreesyncVideo && pipe->stream->adjust.v_total_min > timing->v_total; ++ ++ if (!isFreesyncVideo) { ++ pipes[pipe_cnt].pipe.dest.vblank_nom = ++ dcn3_14_ip.VBlankNomDefaultUS / (timing->h_total / (timing->pix_clk_100hz / 10000.0)); ++ } else { ++ pipes[pipe_cnt].pipe.dest.vtotal = pipe->stream->adjust.v_total_min; ++ pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; ++ } + + if (pipe->plane_state && + (pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height || +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Rework-comments-on-dc-file.patch b/patches.suse/drm-amd-display-Rework-comments-on-dc-file.patch new file mode 100644 index 0000000..68754cb --- /dev/null +++ b/patches.suse/drm-amd-display-Rework-comments-on-dc-file.patch @@ -0,0 +1,376 @@ +From e366f36958f60c431a7430c8c421c9db0ec6738d Mon Sep 17 00:00:00 2001 +From: Rodrigo Siqueira +Date: Tue, 18 Oct 2022 16:27:59 -0400 +Subject: [PATCH] drm/amd/display: Rework comments on dc file +Git-commit: e366f36958f60c431a7430c8c421c9db0ec6738d +Patch-mainline: v6.2-rc1 +References: git-fixes + +The file dc.c has multiple comments that do not follow the kernel-doc or +are made in a distracting way. This commit alleviates part of this issue +by reorganizing some comments inside the dc file. + +Signed-off-by: Rodrigo Siqueira +Reviewed-by: Hamza Mahfooz +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dc/core/dc.c | 161 +++++++++-------------- + drivers/gpu/drm/amd/display/dc/dc.h | 32 ++--- + 2 files changed, 70 insertions(+), 123 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index 2858917a66be..d446e6098948 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -135,9 +135,7 @@ static const char DC_BUILD_ID[] = "production-build"; + * one or two (in the pipe-split case). + */ + +-/******************************************************************************* +- * Private functions +- ******************************************************************************/ ++/* Private functions */ + + static inline void elevate_update_type(enum surface_update_type *original, enum surface_update_type new) + { +@@ -421,18 +419,14 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc, + } + + /** +- ***************************************************************************** +- * Function: dc_stream_get_last_vrr_vtotal ++ * dc_stream_get_last_used_drr_vtotal - dc_stream_get_last_vrr_vtotal + * +- * @brief +- * Looks up the pipe context of dc_stream_state and gets the +- * last VTOTAL used by DRR (Dynamic Refresh Rate) ++ * @dc: [in] dc reference ++ * @stream: [in] Initial dc stream state ++ * @adjust: [in] Updated parameters for vertical_total_min and + * +- * @param [in] dc: dc reference +- * @param [in] stream: Initial dc stream state +- * @param [in] adjust: Updated parameters for vertical_total_min and +- * vertical_total_max +- ***************************************************************************** ++ * Looks up the pipe context of dc_stream_state and gets the last VTOTAL used ++ * by DRR (Dynamic Refresh Rate) + */ + bool dc_stream_get_last_used_drr_vtotal(struct dc *dc, + struct dc_stream_state *stream, +@@ -1209,9 +1203,7 @@ static void wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context) + PERF_TRACE(); + } + +-/******************************************************************************* +- * Public functions +- ******************************************************************************/ ++/* Public functions */ + + struct dc *dc_create(const struct dc_init_data *init_params) + { +@@ -4552,21 +4544,17 @@ void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc) + dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down = true; + } + +-/* +- ***************************************************************************** +- * Function: dc_is_dmub_outbox_supported - ++/** ++ * dc_is_dmub_outbox_supported - Check if DMUB firmware support outbox notification + * +- * @brief +- * Checks whether DMUB FW supports outbox notifications, if supported +- * DM should register outbox interrupt prior to actually enabling interrupts +- * via dc_enable_dmub_outbox ++ * @dc: [in] dc structure + * +- * @param +- * [in] dc: dc structure ++ * Checks whether DMUB FW supports outbox notifications, if supported DM ++ * should register outbox interrupt prior to actually enabling interrupts ++ * via dc_enable_dmub_outbox + * +- * @return +- * True if DMUB FW supports outbox notifications, False otherwise +- ***************************************************************************** ++ * Return: ++ * True if DMUB FW supports outbox notifications, False otherwise + */ + bool dc_is_dmub_outbox_supported(struct dc *dc) + { +@@ -4584,21 +4572,17 @@ bool dc_is_dmub_outbox_supported(struct dc *dc) + return dc->debug.enable_dmub_aux_for_legacy_ddc; + } + +-/* +- ***************************************************************************** +- * Function: dc_enable_dmub_notifications ++/** ++ * dc_enable_dmub_notifications - Check if dmub fw supports outbox + * +- * @brief +- * Calls dc_is_dmub_outbox_supported to check if dmub fw supports outbox +- * notifications. All DMs shall switch to dc_is_dmub_outbox_supported. +- * This API shall be removed after switching. ++ * @dc: [in] dc structure + * +- * @param +- * [in] dc: dc structure ++ * Calls dc_is_dmub_outbox_supported to check if dmub fw supports outbox ++ * notifications. All DMs shall switch to dc_is_dmub_outbox_supported. This ++ * API shall be removed after switching. + * +- * @return +- * True if DMUB FW supports outbox notifications, False otherwise +- ***************************************************************************** ++ * Return: ++ * True if DMUB FW supports outbox notifications, False otherwise + */ + bool dc_enable_dmub_notifications(struct dc *dc) + { +@@ -4606,18 +4590,11 @@ bool dc_enable_dmub_notifications(struct dc *dc) + } + + /** +- ***************************************************************************** +- * Function: dc_enable_dmub_outbox ++ * dc_enable_dmub_outbox - Enables DMUB unsolicited notification + * +- * @brief +- * Enables DMUB unsolicited notifications to x86 via outbox ++ * dc: [in] dc structure + * +- * @param +- * [in] dc: dc structure +- * +- * @return +- * None +- ***************************************************************************** ++ * Enables DMUB unsolicited notifications to x86 via outbox. + */ + void dc_enable_dmub_outbox(struct dc *dc) + { +@@ -4718,21 +4695,17 @@ uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, + } + + /** +- ***************************************************************************** +- * Function: dc_process_dmub_set_config_async ++ * dc_process_dmub_set_config_async - Submits set_config command + * +- * @brief +- * Submits set_config command to dmub via inbox message ++ * @dc: [in] dc structure ++ * @link_index: [in] link_index: link index ++ * @payload: [in] aux payload ++ * @notify: [out] set_config immediate reply + * +- * @param +- * [in] dc: dc structure +- * [in] link_index: link index +- * [in] payload: aux payload +- * [out] notify: set_config immediate reply ++ * Submits set_config command to dmub via inbox message. + * +- * @return +- * True if successful, False if failure +- ***************************************************************************** ++ * Return: ++ * True if successful, False if failure + */ + bool dc_process_dmub_set_config_async(struct dc *dc, + uint32_t link_index, +@@ -4768,21 +4741,17 @@ bool dc_process_dmub_set_config_async(struct dc *dc, + } + + /** +- ***************************************************************************** +- * Function: dc_process_dmub_set_mst_slots ++ * dc_process_dmub_set_mst_slots - Submits MST solt allocation + * +- * @brief +- * Submits mst slot allocation command to dmub via inbox message ++ * @dc: [in] dc structure ++ * @link_index: [in] link index ++ * @mst_alloc_slots: [in] mst slots to be allotted ++ * @mst_slots_in_use: [out] mst slots in use returned in failure case + * +- * @param +- * [in] dc: dc structure +- * [in] link_index: link index +- * [in] mst_alloc_slots: mst slots to be allotted +- * [out] mst_slots_in_use: mst slots in use returned in failure case ++ * Submits mst slot allocation command to dmub via inbox message + * +- * @return +- * DC_OK if successful, DC_ERROR if failure +- ***************************************************************************** ++ * Return: ++ * DC_OK if successful, DC_ERROR if failure + */ + enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, + uint32_t link_index, +@@ -4822,19 +4791,12 @@ enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, + } + + /** +- ***************************************************************************** +- * Function: dc_process_dmub_dpia_hpd_int_enable ++ * dc_process_dmub_dpia_hpd_int_enable - Submits DPIA DPD interruption + * +- * @brief +- * Submits dpia hpd int enable command to dmub via inbox message ++ * @dc [in]: dc structure ++ * @hpd_int_enable [in]: 1 for hpd int enable, 0 to disable + * +- * @param +- * [in] dc: dc structure +- * [in] hpd_int_enable: 1 for hpd int enable, 0 to disable +- * +- * @return +- * None +- ***************************************************************************** ++ * Submits dpia hpd int enable command to dmub via inbox message + */ + void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, + uint32_t hpd_int_enable) +@@ -4863,16 +4825,13 @@ void dc_disable_accelerated_mode(struct dc *dc) + + + /** +- ***************************************************************************** +- * dc_notify_vsync_int_state() - notifies vsync enable/disable state ++ * dc_notify_vsync_int_state - notifies vsync enable/disable state + * @dc: dc structure +- * @stream: stream where vsync int state changed +- * @enable: whether vsync is enabled or disabled ++ * @stream: stream where vsync int state changed ++ * @enable: whether vsync is enabled or disabled + * +- * Called when vsync is enabled/disabled +- * Will notify DMUB to start/stop ABM interrupts after steady state is reached +- * +- ***************************************************************************** ++ * Called when vsync is enabled/disabled Will notify DMUB to start/stop ABM ++ * interrupts after steady state is reached. + */ + void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable) + { +@@ -4914,14 +4873,18 @@ void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bo + if (pipe->stream_res.abm && pipe->stream_res.abm->funcs->set_abm_pause) + pipe->stream_res.abm->funcs->set_abm_pause(pipe->stream_res.abm, !enable, i, pipe->stream_res.tg->inst); + } +-/* +- * dc_extended_blank_supported: Decide whether extended blank is supported ++ ++/** ++ * dc_extended_blank_supported 0 Decide whether extended blank is supported + * +- * Extended blank is a freesync optimization feature to be enabled in the future. +- * During the extra vblank period gained from freesync, we have the ability to enter z9/z10. ++ * @dc: [in] Current DC state + * +- * @param [in] dc: Current DC state +- * @return: Indicate whether extended blank is supported (true or false) ++ * Extended blank is a freesync optimization feature to be enabled in the ++ * future. During the extra vblank period gained from freesync, we have the ++ * ability to enter z9/z10. ++ * ++ * Return: ++ * Indicate whether extended blank is supported (true or false) + */ + bool dc_extended_blank_supported(struct dc *dc) + { +diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h +index c43bafa289e6..2a6406440032 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc.h ++++ b/drivers/gpu/drm/amd/display/dc/dc.h +@@ -56,9 +56,7 @@ struct dmub_notification; + #define MIN_VIEWPORT_SIZE 12 + #define MAX_NUM_EDP 2 + +-/******************************************************************************* +- * Display Core Interfaces +- ******************************************************************************/ ++/* Display Core Interfaces */ + struct dc_versions { + const char *dc_ver; + struct dmcu_version dmcu_version; +@@ -1000,9 +998,7 @@ void dc_init_callbacks(struct dc *dc, + void dc_deinit_callbacks(struct dc *dc); + void dc_destroy(struct dc **dc); + +-/******************************************************************************* +- * Surface Interfaces +- ******************************************************************************/ ++/* Surface Interfaces */ + + enum { + TRANSFER_FUNC_POINTS = 1025 +@@ -1363,9 +1359,7 @@ struct dc_state *dc_copy_state(struct dc_state *src_ctx); + void dc_retain_state(struct dc_state *context); + void dc_release_state(struct dc_state *context); + +-/******************************************************************************* +- * Link Interfaces +- ******************************************************************************/ ++/* Link Interfaces */ + + struct dpcd_caps { + union dpcd_rev dpcd_rev; +@@ -1467,9 +1461,7 @@ struct hdcp_caps { + + uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); + +-/******************************************************************************* +- * Sink Interfaces - A sink corresponds to a display output device +- ******************************************************************************/ ++/* Sink Interfaces - A sink corresponds to a display output device */ + + struct dc_container_id { + // 128bit GUID in binary form +@@ -1552,9 +1544,7 @@ struct dc_cursor { + }; + + +-/******************************************************************************* +- * Interrupt interfaces +- ******************************************************************************/ ++/* Interrupt interfaces */ + enum dc_irq_source dc_interrupt_to_irq_source( + struct dc *dc, + uint32_t src_id, +@@ -1566,9 +1556,7 @@ enum dc_irq_source dc_get_hpd_irq_source_at_index( + + void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); + +-/******************************************************************************* +- * Power Interfaces +- ******************************************************************************/ ++/* Power Interfaces */ + + void dc_set_power_state( + struct dc *dc, +@@ -1641,14 +1629,10 @@ enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, + void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, + uint32_t hpd_int_enable); + +-/******************************************************************************* +- * DSC Interfaces +- ******************************************************************************/ ++/* DSC Interfaces */ + #include "dc_dsc.h" + +-/******************************************************************************* +- * Disable acc mode Interfaces +- ******************************************************************************/ ++/* Disable acc mode Interfaces */ + void dc_disable_accelerated_mode(struct dc *dc); + + #endif /* DC_INTERFACE_H_ */ +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Rework-context-change-check.patch b/patches.suse/drm-amd-display-Rework-context-change-check.patch new file mode 100644 index 0000000..18202b1 --- /dev/null +++ b/patches.suse/drm-amd-display-Rework-context-change-check.patch @@ -0,0 +1,66 @@ +From 10fdb0a11c555e0d6f7698d2874581d06e99ee71 Mon Sep 17 00:00:00 2001 +From: Rodrigo Siqueira +Date: Tue, 18 Oct 2022 08:28:16 -0400 +Subject: [PATCH] drm/amd/display: Rework context change check +Git-commit: 10fdb0a11c555e0d6f7698d2874581d06e99ee71 +Patch-mainline: v6.2-rc1 +References: git-fixes + +Context change is all about streams; for this reason, this commit +renames context_changed to streams_changed. Additionally, to make this +function more flexible, this commit changes the function signature to +receive the stream array and the stream count as a parameter. + +Reviewed-by: Harry Wentland +Signed-off-by: Rodrigo Siqueira +Co-developed-by: Aurabindo Pillai +Signed-off-by: Aurabindo Pillai +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dc/core/dc.c | 14 +++++++------- + 1 file changed, 7 insertions(+), 7 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index 7b576bd24cb5..9219d1efde2a 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -1488,19 +1488,19 @@ static void program_timing_sync( + } + } + +-static bool context_changed( +- struct dc *dc, +- struct dc_state *context) ++static bool streams_changed(struct dc *dc, ++ struct dc_stream_state *streams[], ++ uint8_t stream_count) + { + uint8_t i; + +- if (context->stream_count != dc->current_state->stream_count) ++ if (stream_count != dc->current_state->stream_count) + return true; + + for (i = 0; i < dc->current_state->stream_count; i++) { +- if (dc->current_state->streams[i] != context->streams[i]) ++ if (dc->current_state->streams[i] != streams[i]) + return true; +- if (!context->streams[i]->link->link_state_valid) ++ if (!streams[i]->link->link_state_valid) + return true; + } + +@@ -1895,7 +1895,7 @@ bool dc_commit_state(struct dc *dc, struct dc_state *context) + enum dc_status result = DC_ERROR_UNEXPECTED; + int i; + +- if (!context_changed(dc, context)) ++ if (!streams_changed(dc, context->streams, context->stream_count)) + return DC_OK; + + DC_LOG_DC("%s: %d streams\n", +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Set-minimum-requirement-for-using-PS-cd2e31a.patch b/patches.suse/drm-amd-display-Set-minimum-requirement-for-using-PS-cd2e31a.patch new file mode 100644 index 0000000..b1cc9bf --- /dev/null +++ b/patches.suse/drm-amd-display-Set-minimum-requirement-for-using-PS-cd2e31a.patch @@ -0,0 +1,68 @@ +From cd2e31a9ab93d13c412a36c6e26811e0f830985b Mon Sep 17 00:00:00 2001 +From: Mario Limonciello +Date: Fri, 23 Jun 2023 10:05:21 -0500 +Subject: [PATCH] drm/amd/display: Set minimum requirement for using PSR-SU on Phoenix +Git-commit: cd2e31a9ab93d13c412a36c6e26811e0f830985b +Patch-mainline: v6.5-rc1 +References: git-fixes + +The same parade TCON issue can potentially happen on Phoenix, and the same +PSR resilience changes have been ported into the DMUB firmware. + +Don't allow running PSR-SU unless on the newer firmware. + +Cc: stable@vger.kernel.org +Cc: Sean Wang +Cc: Marc Rossi +Cc: Hamza Mahfooz +Cc: Tsung-hua (Ryan) Lin +Signed-off-by: Mario Limonciello +Reviewed-by: Leo Li +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dmub/src/dmub_dcn314.c | 5 +++++ + drivers/gpu/drm/amd/display/dmub/src/dmub_dcn314.h | 2 ++ + drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 1 + + 3 files changed, 8 insertions(+) + +diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn314.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn314.c +index 48a06dbd9be7..f161aeb7e7c4 100644 +--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn314.c ++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn314.c +@@ -60,3 +60,8 @@ const struct dmub_srv_dcn31_regs dmub_srv_dcn314_regs = { + { DMUB_DCN31_FIELDS() }, + #undef DMUB_SF + }; ++ ++bool dmub_dcn314_is_psrsu_supported(struct dmub_srv *dmub) ++{ ++ return dmub->fw_version >= DMUB_FW_VERSION(8, 0, 16); ++} +diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn314.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn314.h +index 674267a2940e..f213bd82c911 100644 +--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn314.h ++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn314.h +@@ -30,4 +30,6 @@ + + extern const struct dmub_srv_dcn31_regs dmub_srv_dcn314_regs; + ++bool dmub_dcn314_is_psrsu_supported(struct dmub_srv *dmub); ++ + #endif /* _DMUB_DCN314_H_ */ +diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +index 7a31e3e27bab..bdaf43892f47 100644 +--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c ++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +@@ -228,6 +228,7 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) + case DMUB_ASIC_DCN316: + if (asic == DMUB_ASIC_DCN314) { + dmub->regs_dcn31 = &dmub_srv_dcn314_regs; ++ funcs->is_psrsu_supported = dmub_dcn314_is_psrsu_supported; + } else if (asic == DMUB_ASIC_DCN315) { + dmub->regs_dcn31 = &dmub_srv_dcn315_regs; + } else if (asic == DMUB_ASIC_DCN316) { +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Set-minimum-requirement-for-using-PS.patch b/patches.suse/drm-amd-display-Set-minimum-requirement-for-using-PS.patch new file mode 100644 index 0000000..2f6b835 --- /dev/null +++ b/patches.suse/drm-amd-display-Set-minimum-requirement-for-using-PS.patch @@ -0,0 +1,134 @@ +From c35b6ea8f2ecfa9d775530b70d4e727869099a9c Mon Sep 17 00:00:00 2001 +From: Mario Limonciello +Date: Fri, 23 Jun 2023 10:05:20 -0500 +Subject: [PATCH] drm/amd/display: Set minimum requirement for using PSR-SU on Rembrandt +Git-commit: c35b6ea8f2ecfa9d775530b70d4e727869099a9c +Patch-mainline: v6.5-rc1 +References: git-fixes + +A number of parade TCONs are causing system hangs when utilized with +older DMUB firmware and PSR-SU. Some changes have been introduced into +DMUB firmware to add resilience against these failures. + +Don't allow running PSR-SU unless on the newer firmware. + +Cc: stable@vger.kernel.org +Cc: Sean Wang +Cc: Marc Rossi +Cc: Hamza Mahfooz +Cc: Tsung-hua (Ryan) Lin +Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2443 +Signed-off-by: Mario Limonciello +Reviewed-by: Leo Li +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 3 ++- + drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 7 +++++++ + drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 1 + + drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 2 ++ + drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c | 5 +++++ + drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h | 2 ++ + drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 10 ++++++---- + 7 files changed, 25 insertions(+), 5 deletions(-) + +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c +@@ -24,6 +24,7 @@ + */ + + #include "amdgpu_dm_psr.h" ++#include "dc_dmub_srv.h" + #include "dc.h" + #include "dm_helpers.h" + #include "amdgpu_dm.h" +@@ -50,7 +51,7 @@ static bool link_supports_psrsu(struct d + !link->dpcd_caps.psr_info.psr2_su_y_granularity_cap) + return false; + +- return true; ++ return dc_dmub_check_min_version(dc->ctx->dmub_srv->dmub); + } + + /* +--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c ++++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c +@@ -1026,3 +1026,10 @@ void dc_send_update_cursor_info_to_dmu( + dc_send_cmd_to_dmu(pCtx->stream->ctx->dmub_srv, &cmd); + } + } ++ ++bool dc_dmub_check_min_version(struct dmub_srv *srv) ++{ ++ if (!srv->hw_funcs.is_psrsu_supported) ++ return true; ++ return srv->hw_funcs.is_psrsu_supported(srv); ++} +--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h ++++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h +@@ -89,4 +89,5 @@ void dc_dmub_setup_subvp_dmub_command(st + void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv); + + void dc_send_update_cursor_info_to_dmu(struct pipe_ctx *pCtx, uint8_t pipe_idx); ++bool dc_dmub_check_min_version(struct dmub_srv *srv); + #endif /* _DMUB_DC_SRV_H_ */ +--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h ++++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h +@@ -358,6 +358,8 @@ struct dmub_srv_hw_funcs { + + bool (*is_supported)(struct dmub_srv *dmub); + ++ bool (*is_psrsu_supported)(struct dmub_srv *dmub); ++ + bool (*is_hw_init)(struct dmub_srv *dmub); + + bool (*is_phy_init)(struct dmub_srv *dmub); +--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c ++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c +@@ -302,6 +302,11 @@ bool dmub_dcn31_is_supported(struct dmub + return supported; + } + ++bool dmub_dcn31_is_psrsu_supported(struct dmub_srv *dmub) ++{ ++ return dmub->fw_version >= DMUB_FW_VERSION(4, 0, 59); ++} ++ + void dmub_dcn31_set_gpint(struct dmub_srv *dmub, + union dmub_gpint_data_register reg) + { +--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h ++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h +@@ -221,6 +221,8 @@ bool dmub_dcn31_is_hw_init(struct dmub_s + + bool dmub_dcn31_is_supported(struct dmub_srv *dmub); + ++bool dmub_dcn31_is_psrsu_supported(struct dmub_srv *dmub); ++ + void dmub_dcn31_set_gpint(struct dmub_srv *dmub, + union dmub_gpint_data_register reg); + +--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c ++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +@@ -228,14 +228,16 @@ static bool dmub_srv_hw_setup(struct dmu + case DMUB_ASIC_DCN314: + case DMUB_ASIC_DCN315: + case DMUB_ASIC_DCN316: +- if (asic == DMUB_ASIC_DCN314) ++ if (asic == DMUB_ASIC_DCN314) { + dmub->regs_dcn31 = &dmub_srv_dcn314_regs; +- else if (asic == DMUB_ASIC_DCN315) ++ } else if (asic == DMUB_ASIC_DCN315) { + dmub->regs_dcn31 = &dmub_srv_dcn315_regs; +- else if (asic == DMUB_ASIC_DCN316) ++ } else if (asic == DMUB_ASIC_DCN316) { + dmub->regs_dcn31 = &dmub_srv_dcn316_regs; +- else ++ } else { + dmub->regs_dcn31 = &dmub_srv_dcn31_regs; ++ funcs->is_psrsu_supported = dmub_dcn31_is_psrsu_supported; ++ } + funcs->reset = dmub_dcn31_reset; + funcs->reset_release = dmub_dcn31_reset_release; + funcs->backdoor_load = dmub_dcn31_backdoor_load; diff --git a/patches.suse/drm-amd-display-Update-OTG-instance-in-the-commit-st.patch b/patches.suse/drm-amd-display-Update-OTG-instance-in-the-commit-st.patch new file mode 100644 index 0000000..637fa53 --- /dev/null +++ b/patches.suse/drm-amd-display-Update-OTG-instance-in-the-commit-st.patch @@ -0,0 +1,45 @@ +From eef019eabc3cd0fddcffefbf67806a4d8cca29bb Mon Sep 17 00:00:00 2001 +From: Rodrigo Siqueira +Date: Tue, 18 Oct 2022 08:28:23 -0400 +Subject: [PATCH] drm/amd/display: Update OTG instance in the commit stream +Git-commit: eef019eabc3cd0fddcffefbf67806a4d8cca29bb +Patch-mainline: v6.2-rc1 +References: git-fixes + +OTG instance is not updated in dc_commit_state_no_check for newly +committed streams because mode_change is not set. Notice that OTG update +is part of the software state, and after hardware programming, it must +be updated; for this reason, this commit updates the OTG offset right +after hardware programming. + +Reviewed-by: Harry Wentland +Signed-off-by: Rodrigo Siqueira +Co-developed-by: Aurabindo Pillai +Signed-off-by: Aurabindo Pillai +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dc/core/dc.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index d568387c4bda..b7afada35b24 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -1949,6 +1949,12 @@ enum dc_status dc_commit_streams(struct dc *dc, + + res = dc_commit_state_no_check(dc, context); + ++ for (i = 0; i < stream_count; i++) { ++ for (j = 0; j < context->stream_count; j++) ++ if (streams[i]->stream_id == context->streams[j]->stream_id) ++ streams[i]->out.otg_offset = context->stream_status[j].primary_otg_inst; ++ } ++ + fail: + dc_release_state(context); + +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Update-correct-DCN314-register-heade.patch b/patches.suse/drm-amd-display-Update-correct-DCN314-register-heade.patch new file mode 100644 index 0000000..6c11909 --- /dev/null +++ b/patches.suse/drm-amd-display-Update-correct-DCN314-register-heade.patch @@ -0,0 +1,176 @@ +From 268182606f26434c5d3ebd0e86efcb0418dec487 Mon Sep 17 00:00:00 2001 +From: Cruise Hung +Date: Fri, 12 May 2023 23:33:46 +0800 +Subject: [PATCH] drm/amd/display: Update correct DCN314 register header +Git-commit: 268182606f26434c5d3ebd0e86efcb0418dec487 +Patch-mainline: v6.5-rc1 +References: git-fixes + +[Why] +The register header for DCN314 is not correct. + +[How] +Update correct DCN314 register header. + +Reviewed-by: Nicholas Kazlauskas +Acked-by: Tom Chung +Signed-off-by: Cruise Hung +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dmub/src/Makefile | 2 +- + .../drm/amd/display/dmub/src/dmub_dcn314.c | 62 +++++++++++++++++++ + .../drm/amd/display/dmub/src/dmub_dcn314.h | 33 ++++++++++ + .../gpu/drm/amd/display/dmub/src/dmub_srv.c | 5 +- + 4 files changed, 100 insertions(+), 2 deletions(-) + create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn314.c + create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn314.h + +diff --git a/drivers/gpu/drm/amd/display/dmub/src/Makefile b/drivers/gpu/drm/amd/display/dmub/src/Makefile +index 0589ad4778ee..caf095aca8f3 100644 +--- a/drivers/gpu/drm/amd/display/dmub/src/Makefile ++++ b/drivers/gpu/drm/amd/display/dmub/src/Makefile +@@ -22,7 +22,7 @@ + + DMUB = dmub_srv.o dmub_srv_stat.o dmub_reg.o dmub_dcn20.o dmub_dcn21.o + DMUB += dmub_dcn30.o dmub_dcn301.o dmub_dcn302.o dmub_dcn303.o +-DMUB += dmub_dcn31.o dmub_dcn315.o dmub_dcn316.o ++DMUB += dmub_dcn31.o dmub_dcn314.o dmub_dcn315.o dmub_dcn316.o + DMUB += dmub_dcn32.o + + AMD_DAL_DMUB = $(addprefix $(AMDDALPATH)/dmub/src/,$(DMUB)) +diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn314.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn314.c +new file mode 100644 +index 000000000000..48a06dbd9be7 +--- /dev/null ++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn314.c +@@ -0,0 +1,62 @@ ++/* ++ * Copyright 2021 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: AMD ++ * ++ */ ++ ++#include "../dmub_srv.h" ++#include "dmub_reg.h" ++#include "dmub_dcn314.h" ++ ++#include "dcn/dcn_3_1_4_offset.h" ++#include "dcn/dcn_3_1_4_sh_mask.h" ++ ++#define DCN_BASE__INST0_SEG0 0x00000012 ++#define DCN_BASE__INST0_SEG1 0x000000C0 ++#define DCN_BASE__INST0_SEG2 0x000034C0 ++#define DCN_BASE__INST0_SEG3 0x00009000 ++#define DCN_BASE__INST0_SEG4 0x02403C00 ++#define DCN_BASE__INST0_SEG5 0 ++ ++#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg ++#define CTX dmub ++#define REGS dmub->regs_dcn31 ++#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name) ++ ++/* Registers. */ ++ ++const struct dmub_srv_dcn31_regs dmub_srv_dcn314_regs = { ++#define DMUB_SR(reg) REG_OFFSET_EXP(reg), ++ { ++ DMUB_DCN31_REGS() ++ DMCUB_INTERNAL_REGS() ++ }, ++#undef DMUB_SR ++ ++#define DMUB_SF(reg, field) FD_MASK(reg, field), ++ { DMUB_DCN31_FIELDS() }, ++#undef DMUB_SF ++ ++#define DMUB_SF(reg, field) FD_SHIFT(reg, field), ++ { DMUB_DCN31_FIELDS() }, ++#undef DMUB_SF ++}; +diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn314.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn314.h +new file mode 100644 +index 000000000000..674267a2940e +--- /dev/null ++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn314.h +@@ -0,0 +1,33 @@ ++/* ++ * Copyright 2021 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: AMD ++ * ++ */ ++ ++#ifndef _DMUB_DCN314_H_ ++#define _DMUB_DCN314_H_ ++ ++#include "dmub_dcn31.h" ++ ++extern const struct dmub_srv_dcn31_regs dmub_srv_dcn314_regs; ++ ++#endif /* _DMUB_DCN314_H_ */ +diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +index ea3bed70a229..9e9a6a44a7ac 100644 +--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c ++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +@@ -32,6 +32,7 @@ + #include "dmub_dcn302.h" + #include "dmub_dcn303.h" + #include "dmub_dcn31.h" ++#include "dmub_dcn314.h" + #include "dmub_dcn315.h" + #include "dmub_dcn316.h" + #include "dmub_dcn32.h" +@@ -225,7 +226,9 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) + case DMUB_ASIC_DCN314: + case DMUB_ASIC_DCN315: + case DMUB_ASIC_DCN316: +- if (asic == DMUB_ASIC_DCN315) ++ if (asic == DMUB_ASIC_DCN314) ++ dmub->regs_dcn31 = &dmub_srv_dcn314_regs; ++ else if (asic == DMUB_ASIC_DCN315) + dmub->regs_dcn31 = &dmub_srv_dcn315_regs; + else if (asic == DMUB_ASIC_DCN316) + dmub->regs_dcn31 = &dmub_srv_dcn316_regs; +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Update-min-Z8-residency-time-to-2100.patch b/patches.suse/drm-amd-display-Update-min-Z8-residency-time-to-2100.patch new file mode 100644 index 0000000..ec082ea --- /dev/null +++ b/patches.suse/drm-amd-display-Update-min-Z8-residency-time-to-2100.patch @@ -0,0 +1,37 @@ +From 4636a211980052ca0df90265c8a3ed2d46099091 Mon Sep 17 00:00:00 2001 +From: Nicholas Kazlauskas +Date: Wed, 8 Nov 2023 10:59:00 -0500 +Subject: [PATCH] drm/amd/display: Update min Z8 residency time to 2100 for DCN314 +Git-commit: 4636a211980052ca0df90265c8a3ed2d46099091 +Patch-mainline: v6.7-rc4 +References: git-fixes + +[Why] +Some panels with residency period of 2054 exhibit flickering with +Z8 at the end of the frame. + +[How] +As a workaround, increase the limit to block these panels. + +Cc: stable@vger.kernel.org # 6.1+ +Reviewed-by: Syed Hassan +Acked-by: Hamza Mahfooz +Signed-off-by: Nicholas Kazlauskas +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c +@@ -884,7 +884,7 @@ static const struct dc_plane_cap plane_c + static const struct dc_debug_options debug_defaults_drv = { + .disable_z10 = false, + .enable_z9_disable_interface = true, +- .minimum_z8_residency_time = 2000, ++ .minimum_z8_residency_time = 2100, + .psr_skip_crtc_disable = true, + .disable_dmcu = true, + .force_abm_enable = false, diff --git a/patches.suse/drm-amd-display-Use-DRAM-speed-from-validation-for-d.patch b/patches.suse/drm-amd-display-Use-DRAM-speed-from-validation-for-d.patch new file mode 100644 index 0000000..242a413 --- /dev/null +++ b/patches.suse/drm-amd-display-Use-DRAM-speed-from-validation-for-d.patch @@ -0,0 +1,49 @@ +From 9be601135ba8ac69880c01606c82140f2dde105e Mon Sep 17 00:00:00 2001 +From: Alvin Lee +Date: Tue, 7 Nov 2023 17:01:49 -0500 +Subject: [PATCH] drm/amd/display: Use DRAM speed from validation for dummy p-state +Git-commit: 9be601135ba8ac69880c01606c82140f2dde105e +Patch-mainline: v6.7-rc4 +References: git-fixes + +[Description] +When choosing which dummy p-state latency to use, we +need to use the DRAM speed from validation. The DRAMSpeed +DML variable can change because we use different input +params to DML when populating watermarks set B. + +Cc: stable@vger.kernel.org # 6.1+ +Reviewed-by: Samson Tam +Acked-by: Hamza Mahfooz +Signed-off-by: Alvin Lee +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +index 44b0666e53b0..b46cde525066 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +@@ -2235,6 +2235,7 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, + int i, pipe_idx, vlevel_temp = 0; + double dcfclk = dcn3_2_soc.clock_limits[0].dcfclk_mhz; + double dcfclk_from_validation = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; ++ double dram_speed_from_validation = context->bw_ctx.dml.vba.DRAMSpeed; + double dcfclk_from_fw_based_mclk_switching = dcfclk_from_validation; + bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != + dm_dram_clock_change_unsupported; +@@ -2422,7 +2423,7 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, + } + + if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { +- min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed; ++ min_dram_speed_mts = dram_speed_from_validation; + min_dram_speed_mts_margin = 160; + + context->bw_ctx.dml.soc.dram_clock_change_latency_us = +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Use-DTBCLK-as-refclk-instead-of-DPRE.patch b/patches.suse/drm-amd-display-Use-DTBCLK-as-refclk-instead-of-DPRE.patch new file mode 100644 index 0000000..891e0c8 --- /dev/null +++ b/patches.suse/drm-amd-display-Use-DTBCLK-as-refclk-instead-of-DPRE.patch @@ -0,0 +1,44 @@ +From 4a30cc2bd281fa176a68b5305cd3695d636152ad Mon Sep 17 00:00:00 2001 +From: Austin Zheng +Date: Wed, 26 Jul 2023 10:40:48 -0400 +Subject: [PATCH] drm/amd/display: Use DTBCLK as refclk instead of DPREFCLK +Git-commit: 4a30cc2bd281fa176a68b5305cd3695d636152ad +Patch-mainline: v6.6-rc1 +References: git-fixes + +[Why] +Flash of corruption observed when UCLK switching after transitioning +from DTBCLK to DPREFCLK on subVP(DP) + subVP(HDMI) config +Scenario where DPREFCLK is required instead of DTBCLK is not expected + +[How] +Always set the DTBCLK source as DTBCLK0 + +Reviewed-by: Alvin Lee +Acked-by: Tom Chung +Signed-off-by: Austin Zheng +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c +index 61ceff6bc0b1..921f58c0c729 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c +@@ -281,7 +281,8 @@ static void dccg32_set_dpstreamclk( + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + /* set the dtbclk_p source */ +- dccg32_set_dtbclk_p_src(dccg, src, otg_inst); ++ /* always program refclk as DTBCLK. No use-case expected to require DPREFCLK as refclk */ ++ dccg32_set_dtbclk_p_src(dccg, DTBCLK0, otg_inst); + + /* enabled to select one of the DTBCLKs for pipe */ + switch (dp_hpo_inst) { +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Use-min-transition-for-all-SubVP-pla.patch b/patches.suse/drm-amd-display-Use-min-transition-for-all-SubVP-pla.patch new file mode 100644 index 0000000..af2131d --- /dev/null +++ b/patches.suse/drm-amd-display-Use-min-transition-for-all-SubVP-pla.patch @@ -0,0 +1,95 @@ +From e4c1b01bc35b04e15782608165aa85b9e1724f7b Mon Sep 17 00:00:00 2001 +From: Alvin Lee +Date: Wed, 2 Nov 2022 12:38:12 -0400 +Subject: [PATCH] drm/amd/display: Use min transition for all SubVP plane add/remove +Git-commit: e4c1b01bc35b04e15782608165aa85b9e1724f7b +Patch-mainline: v6.2-rc1 +References: git-fixes + +[Description] +- Whenever disabling a phantom pipe, we must run through the + minimal transition sequence +- In the case where SetVisibility = false for the main pipe, + we also need to run through the min transtion when disabling + the phantom pipes + +Reviewed-by: Jun Lei +Acked-by: Tom Chung +Signed-off-by: Alvin Lee +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dc/core/dc.c | 31 +++++++++++++++++------- + 1 file changed, 22 insertions(+), 9 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index d90ab1867ed7..0a252a65a678 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -3749,17 +3749,17 @@ static bool could_mpcc_tree_change_for_active_pipes(struct dc *dc, + } + } + +- /* For SubVP when adding MPO video we need to add a minimal transition. ++ /* For SubVP when adding or removing planes we need to add a minimal transition ++ * (even when disabling all planes). Whenever disabling a phantom pipe, we ++ * must use the minimal transition path to disable the pipe correctly. + */ + if (cur_stream_status && stream->mall_stream_config.type == SUBVP_MAIN) { + /* determine if minimal transition is required due to SubVP*/ +- if (surface_count > 0) { +- if (cur_stream_status->plane_count > surface_count) { +- force_minimal_pipe_splitting = true; +- } else if (cur_stream_status->plane_count < surface_count) { +- force_minimal_pipe_splitting = true; +- *is_plane_addition = true; +- } ++ if (cur_stream_status->plane_count > surface_count) { ++ force_minimal_pipe_splitting = true; ++ } else if (cur_stream_status->plane_count < surface_count) { ++ force_minimal_pipe_splitting = true; ++ *is_plane_addition = true; + } + } + +@@ -3794,6 +3794,7 @@ static bool commit_minimal_transition_state(struct dc *dc, + enum dc_status ret = DC_ERROR_UNEXPECTED; + unsigned int i, j; + unsigned int pipe_in_use = 0; ++ bool subvp_in_use = false; + + if (!transition_context) + return false; +@@ -3810,6 +3811,18 @@ static bool commit_minimal_transition_state(struct dc *dc, + pipe_in_use++; + } + ++ /* If SubVP is enabled and we are adding or removing planes from any main subvp ++ * pipe, we must use the minimal transition. ++ */ ++ for (i = 0; i < dc->res_pool->pipe_count; i++) { ++ struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; ++ ++ if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { ++ subvp_in_use = true; ++ break; ++ } ++ } ++ + /* When the OS add a new surface if we have been used all of pipes with odm combine + * and mpc split feature, it need use commit_minimal_transition_state to transition safely. + * After OS exit MPO, it will back to use odm and mpc split with all of pipes, we need +@@ -3818,7 +3831,7 @@ static bool commit_minimal_transition_state(struct dc *dc, + * Reduce the scenarios to use dc_commit_state_no_check in the stage of flip. Especially + * enter/exit MPO when DCN still have enough resources. + */ +- if (pipe_in_use != dc->res_pool->pipe_count) { ++ if (pipe_in_use != dc->res_pool->pipe_count && !subvp_in_use) { + dc_release_state(transition_context); + return true; + } +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Write-to-correct-dirty_rect.patch b/patches.suse/drm-amd-display-Write-to-correct-dirty_rect.patch new file mode 100644 index 0000000..3c96f11 --- /dev/null +++ b/patches.suse/drm-amd-display-Write-to-correct-dirty_rect.patch @@ -0,0 +1,49 @@ +From 751281c55579f0cb0e56c9797d4663f689909681 Mon Sep 17 00:00:00 2001 +From: Benjamin Cheng +Date: Sun, 12 Mar 2023 20:47:39 -0400 +Subject: [PATCH] drm/amd/display: Write to correct dirty_rect +Git-commit: 751281c55579f0cb0e56c9797d4663f689909681 +Alt-commit: 566b6577849fcca743aa63d43793062aba62166c +Patch-mainline: v6.3-rc3 +References: git-fixes + +When FB_DAMAGE_CLIPS are provided in a non-MPO scenario, the loop does +not use the counter i. This causes the fill_dc_dity_rect() to always +fill dirty_rects[0], causing graphical artifacts when a damage clip +aware DRM client sends more than 1 damage clip. + +Instead, use the flip_addrs->dirty_rect_count which is incremented by +fill_dc_dirty_rect() on a successful fill. + +Fixes: 30ebe41582d1 ("drm/amd/display: add FB_DAMAGE_CLIPS support") +Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2453 +Signed-off-by: Benjamin Cheng +Signed-off-by: Hamza Mahfooz +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org # 6.1.x +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +index 009ef917dad4..32abbafd43fa 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -5105,9 +5105,9 @@ static void fill_dc_dirty_rects(struct drm_plane *plane, + + for (; flip_addrs->dirty_rect_count < num_clips; clips++) + fill_dc_dirty_rect(new_plane_state->plane, +- &dirty_rects[i], clips->x1, +- clips->y1, clips->x2 - clips->x1, +- clips->y2 - clips->y1, ++ &dirty_rects[flip_addrs->dirty_rect_count], ++ clips->x1, clips->y1, ++ clips->x2 - clips->x1, clips->y2 - clips->y1, + &flip_addrs->dirty_rect_count, + false); + return; +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-Wrong-colorimetry-workaround.patch b/patches.suse/drm-amd-display-Wrong-colorimetry-workaround.patch new file mode 100644 index 0000000..615de94 --- /dev/null +++ b/patches.suse/drm-amd-display-Wrong-colorimetry-workaround.patch @@ -0,0 +1,118 @@ +From b1a98cf89a695d36c414653634ea7ba91b6e701f Mon Sep 17 00:00:00 2001 +From: Ma Hanghong +Date: Thu, 20 Oct 2022 11:46:56 -0400 +Subject: [PATCH] drm/amd/display: Wrong colorimetry workaround +Git-commit: b1a98cf89a695d36c414653634ea7ba91b6e701f +Patch-mainline: v6.2-rc1 +References: git-fixes + +[Why] +For FreeSync HDR, native color space flag in AMD VSIF(BT.709) should be +used when intepreting content and color space flag in VSC or AVI +infoFrame should be ignored. However, it turned out some userspace +application still use color flag in VSC or AVI infoFrame which is +incorrect. + +[How] +Transfer function is used when building the VSC and AVI infoFrame. Set +colorimetry to BT.709 when all the following match: + +1. Pixel format is YCbCr; +2. In FreeSync 2 HDR, color is COLOR_SPACE_2020_YCBCR; +3. Transfer function is TRANSFER_FUNC_GAMMA_22; + +Tested-by: Mark Broadworth +Reviewed-by: Krunoslav Kovac +Acked-by: Rodrigo Siqueira +Signed-off-by: Ma Hanghong +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 ++++- + drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 6 ++++++ + drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h | 3 ++- + .../gpu/drm/amd/display/modules/info_packet/info_packet.c | 6 +++++- + 4 files changed, 17 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +index 72aede3fcf9b..d14e57b19066 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -5697,6 +5697,7 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, + bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false; + int mode_refresh; + int preferred_refresh = 0; ++ enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN; + #if defined(CONFIG_DRM_AMD_DC_DCN) + struct dsc_dec_dpcd_caps dsc_caps; + #endif +@@ -5820,7 +5821,9 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, + if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) + stream->use_vsc_sdp_for_colorimetry = true; + } +- mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space); ++ if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) ++ tf = TRANSFER_FUNC_GAMMA_22; ++ mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf); + aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY; + + } +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +index ba2d4347f722..d99f1c4b9584 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +@@ -3015,6 +3015,12 @@ static void set_avi_info_frame( + hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED; + } + ++ if (pixel_encoding && color_space == COLOR_SPACE_2020_YCBCR && ++ stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) { ++ hdmi_info.bits.EC0_EC2 = 0; ++ hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709; ++ } ++ + /* TODO: un-hardcode aspect ratio */ + aspect = stream->timing.aspect_ratio; + +diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h b/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h +index 1d8b746b02f2..edf5845f6a1f 100644 +--- a/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h ++++ b/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h +@@ -35,7 +35,8 @@ struct mod_vrr_params; + + void mod_build_vsc_infopacket(const struct dc_stream_state *stream, + struct dc_info_packet *info_packet, +- enum dc_color_space cs); ++ enum dc_color_space cs, ++ enum color_transfer_func tf); + + void mod_build_hf_vsif_infopacket(const struct dc_stream_state *stream, + struct dc_info_packet *info_packet); +diff --git a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c +index 27ceba9d6d65..69691058ab89 100644 +--- a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c ++++ b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c +@@ -132,7 +132,8 @@ enum ColorimetryYCCDP { + + void mod_build_vsc_infopacket(const struct dc_stream_state *stream, + struct dc_info_packet *info_packet, +- enum dc_color_space cs) ++ enum dc_color_space cs, ++ enum color_transfer_func tf) + { + unsigned int vsc_packet_revision = vsc_packet_undefined; + unsigned int i; +@@ -382,6 +383,9 @@ void mod_build_vsc_infopacket(const struct dc_stream_state *stream, + colorimetryFormat = ColorimetryYCC_DP_AdobeYCC; + else if (cs == COLOR_SPACE_2020_YCBCR) + colorimetryFormat = ColorimetryYCC_DP_ITU2020YCbCr; ++ ++ if (cs == COLOR_SPACE_2020_YCBCR && tf == TRANSFER_FUNC_GAMMA_22) ++ colorimetryFormat = ColorimetryYCC_DP_ITU709; + break; + + default: +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-add-FB_DAMAGE_CLIPS-support.patch b/patches.suse/drm-amd-display-add-FB_DAMAGE_CLIPS-support.patch new file mode 100644 index 0000000..3f2f5f8 --- /dev/null +++ b/patches.suse/drm-amd-display-add-FB_DAMAGE_CLIPS-support.patch @@ -0,0 +1,225 @@ +From 30ebe41582d1ea5a7de990319f9e593dad4886f7 Mon Sep 17 00:00:00 2001 +From: Hamza Mahfooz +Date: Tue, 15 Nov 2022 11:58:45 -0500 +Subject: [PATCH] drm/amd/display: add FB_DAMAGE_CLIPS support +Git-commit: 30ebe41582d1ea5a7de990319f9e593dad4886f7 +Patch-mainline: v6.2-rc1 +References: git-fixes + +Currently, userspace doesn't have a way to communicate selective updates +to displays. So, enable support for FB_DAMAGE_CLIPS for DCN ASICs newer +than DCN301, convert DRM damage clips to dc dirty rectangles and fill +them into dirty_rects in fill_dc_dirty_rects(). + +Reviewed-by: Leo Li +Signed-off-by: Hamza Mahfooz +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 128 ++++++++++++------ + .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 4 + + 2 files changed, 87 insertions(+), 45 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +index 3934f370a1c2..77277d90b6e2 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -4869,6 +4869,35 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev, + return 0; + } + ++static inline void fill_dc_dirty_rect(struct drm_plane *plane, ++ struct rect *dirty_rect, int32_t x, ++ int32_t y, int32_t width, int32_t height, ++ int *i, bool ffu) ++{ ++ if (*i > DC_MAX_DIRTY_RECTS) ++ return; ++ ++ if (*i == DC_MAX_DIRTY_RECTS) ++ goto out; ++ ++ dirty_rect->x = x; ++ dirty_rect->y = y; ++ dirty_rect->width = width; ++ dirty_rect->height = height; ++ ++ if (ffu) ++ drm_dbg(plane->dev, ++ "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n", ++ plane->base.id, width, height); ++ else ++ drm_dbg(plane->dev, ++ "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)", ++ plane->base.id, x, y, width, height); ++ ++out: ++ (*i)++; ++} ++ + /** + * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates + * +@@ -4889,10 +4918,6 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev, + * addition, certain use cases - such as cursor and multi-plane overlay (MPO) - + * implicitly provide damage clips without any client support via the plane + * bounds. +- * +- * Today, amdgpu_dm only supports the MPO and cursor usecase. +- * +- * TODO: Also enable for FB_DAMAGE_CLIPS + */ + static void fill_dc_dirty_rects(struct drm_plane *plane, + struct drm_plane_state *old_plane_state, +@@ -4903,12 +4928,11 @@ static void fill_dc_dirty_rects(struct drm_plane *plane, + struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); + struct rect *dirty_rects = flip_addrs->dirty_rects; + uint32_t num_clips; ++ struct drm_mode_rect *clips; + bool bb_changed; + bool fb_changed; + uint32_t i = 0; + +- flip_addrs->dirty_rect_count = 0; +- + /* + * Cursor plane has it's own dirty rect update interface. See + * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data +@@ -4916,20 +4940,20 @@ static void fill_dc_dirty_rects(struct drm_plane *plane, + if (plane->type == DRM_PLANE_TYPE_CURSOR) + return; + +- /* +- * Today, we only consider MPO use-case for PSR SU. If MPO not +- * requested, and there is a plane update, do FFU. +- */ ++ num_clips = drm_plane_get_damage_clips_count(new_plane_state); ++ clips = drm_plane_get_damage_clips(new_plane_state); ++ + if (!dm_crtc_state->mpo_requested) { +- dirty_rects[0].x = 0; +- dirty_rects[0].y = 0; +- dirty_rects[0].width = dm_crtc_state->base.mode.crtc_hdisplay; +- dirty_rects[0].height = dm_crtc_state->base.mode.crtc_vdisplay; +- flip_addrs->dirty_rect_count = 1; +- DRM_DEBUG_DRIVER("[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n", +- new_plane_state->plane->base.id, +- dm_crtc_state->base.mode.crtc_hdisplay, +- dm_crtc_state->base.mode.crtc_vdisplay); ++ if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS) ++ goto ffu; ++ ++ for (; flip_addrs->dirty_rect_count < num_clips; clips++) ++ fill_dc_dirty_rect(new_plane_state->plane, ++ &dirty_rects[i], clips->x1, ++ clips->y1, clips->x2 - clips->x1, ++ clips->y2 - clips->y1, ++ &flip_addrs->dirty_rect_count, ++ false); + return; + } + +@@ -4940,7 +4964,6 @@ static void fill_dc_dirty_rects(struct drm_plane *plane, + * If plane is moved or resized, also add old bounding box to dirty + * rects. + */ +- num_clips = drm_plane_get_damage_clips_count(new_plane_state); + fb_changed = old_plane_state->fb->base.id != + new_plane_state->fb->base.id; + bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x || +@@ -4948,36 +4971,51 @@ static void fill_dc_dirty_rects(struct drm_plane *plane, + old_plane_state->crtc_w != new_plane_state->crtc_w || + old_plane_state->crtc_h != new_plane_state->crtc_h); + +- DRM_DEBUG_DRIVER("[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n", +- new_plane_state->plane->base.id, +- bb_changed, fb_changed, num_clips); ++ drm_dbg(plane->dev, ++ "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n", ++ new_plane_state->plane->base.id, ++ bb_changed, fb_changed, num_clips); + +- if (num_clips || fb_changed || bb_changed) { +- dirty_rects[i].x = new_plane_state->crtc_x; +- dirty_rects[i].y = new_plane_state->crtc_y; +- dirty_rects[i].width = new_plane_state->crtc_w; +- dirty_rects[i].height = new_plane_state->crtc_h; +- DRM_DEBUG_DRIVER("[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)\n", +- new_plane_state->plane->base.id, +- dirty_rects[i].x, dirty_rects[i].y, +- dirty_rects[i].width, dirty_rects[i].height); +- i += 1; +- } +- +- /* Add old plane bounding-box if plane is moved or resized */ + if (bb_changed) { +- dirty_rects[i].x = old_plane_state->crtc_x; +- dirty_rects[i].y = old_plane_state->crtc_y; +- dirty_rects[i].width = old_plane_state->crtc_w; +- dirty_rects[i].height = old_plane_state->crtc_h; +- DRM_DEBUG_DRIVER("[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)\n", +- old_plane_state->plane->base.id, +- dirty_rects[i].x, dirty_rects[i].y, +- dirty_rects[i].width, dirty_rects[i].height); +- i += 1; ++ fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], ++ new_plane_state->crtc_x, ++ new_plane_state->crtc_y, ++ new_plane_state->crtc_w, ++ new_plane_state->crtc_h, &i, false); ++ ++ /* Add old plane bounding-box if plane is moved or resized */ ++ fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], ++ old_plane_state->crtc_x, ++ old_plane_state->crtc_y, ++ old_plane_state->crtc_w, ++ old_plane_state->crtc_h, &i, false); + } + ++ if (num_clips) { ++ for (; i < num_clips; clips++) ++ fill_dc_dirty_rect(new_plane_state->plane, ++ &dirty_rects[i], clips->x1, ++ clips->y1, clips->x2 - clips->x1, ++ clips->y2 - clips->y1, &i, false); ++ } else if (fb_changed && !bb_changed) { ++ fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], ++ new_plane_state->crtc_x, ++ new_plane_state->crtc_y, ++ new_plane_state->crtc_w, ++ new_plane_state->crtc_h, &i, false); ++ } ++ ++ if (i > DC_MAX_DIRTY_RECTS) ++ goto ffu; ++ + flip_addrs->dirty_rect_count = i; ++ return; ++ ++ffu: ++ fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0, ++ dm_crtc_state->base.mode.crtc_hdisplay, ++ dm_crtc_state->base.mode.crtc_vdisplay, ++ &flip_addrs->dirty_rect_count, true); + } + + static void update_stream_scaling_settings(const struct drm_display_mode *mode, +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +index e6854f7270a6..3c50b3ff7954 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +@@ -1600,6 +1600,10 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, + drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, + supported_rotations); + ++ if (dm->adev->ip_versions[DCE_HWIP][0] > IP_VERSION(3, 0, 1) && ++ plane->type != DRM_PLANE_TYPE_CURSOR) ++ drm_plane_enable_fb_damage_clips(plane); ++ + drm_plane_helper_add(plane, &dm_plane_helper_funcs); + + #ifdef CONFIG_DRM_AMD_DC_HDR +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-add-ODM-case-when-looking-for-first-.patch b/patches.suse/drm-amd-display-add-ODM-case-when-looking-for-first-.patch new file mode 100644 index 0000000..085c624 --- /dev/null +++ b/patches.suse/drm-amd-display-add-ODM-case-when-looking-for-first-.patch @@ -0,0 +1,151 @@ +From 59de751e3845d699e02dc4da47322b92d83a41e2 Mon Sep 17 00:00:00 2001 +From: Samson Tam +Date: Tue, 9 May 2023 16:40:19 -0400 +Subject: [PATCH] drm/amd/display: add ODM case when looking for first split pipe +Git-commit: 59de751e3845d699e02dc4da47322b92d83a41e2 +Patch-mainline: v6.4-rc6 +References: git-fixes + +[Why] +When going from ODM 2:1 single display case to max displays, second +odm pipe needs to be repurposed for one of the new single displays. +However, acquire_first_split_pipe() only handles MPC case and not +ODM case + +[How] +Add ODM conditions in acquire_first_split_pipe() +Add commit_minimal_transition_state() in commit_streams() to handle +odm 2:1 exit first, and then process new streams +Handle ODM condition in commit_minimal_transition_state() + +Cc: Mario Limonciello +Cc: Alex Deucher +Cc: stable@vger.kernel.org +Acked-by: Stylon Wang +Signed-off-by: Samson Tam +Reviewed-by: Alvin Lee +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dc/core/dc.c | 36 ++++++++++++++++++- + .../gpu/drm/amd/display/dc/core/dc_resource.c | 20 +++++++++++ + 2 files changed, 55 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index 52564b93f7eb..7cde67b7f0c3 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -1981,6 +1981,9 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c + return result; + } + ++static bool commit_minimal_transition_state(struct dc *dc, ++ struct dc_state *transition_base_context); ++ + /** + * dc_commit_streams - Commit current stream state + * +@@ -2002,6 +2005,8 @@ enum dc_status dc_commit_streams(struct dc *dc, + struct dc_state *context; + enum dc_status res = DC_OK; + struct dc_validation_set set[MAX_STREAMS] = {0}; ++ struct pipe_ctx *pipe; ++ bool handle_exit_odm2to1 = false; + + if (dc->ctx->dce_environment == DCE_ENV_VIRTUAL_HW) + return res; +@@ -2026,6 +2031,22 @@ enum dc_status dc_commit_streams(struct dc *dc, + } + } + ++ /* Check for case where we are going from odm 2:1 to max ++ * pipe scenario. For these cases, we will call ++ * commit_minimal_transition_state() to exit out of odm 2:1 ++ * first before processing new streams ++ */ ++ if (stream_count == dc->res_pool->pipe_count) { ++ for (i = 0; i < dc->res_pool->pipe_count; i++) { ++ pipe = &dc->current_state->res_ctx.pipe_ctx[i]; ++ if (pipe->next_odm_pipe) ++ handle_exit_odm2to1 = true; ++ } ++ } ++ ++ if (handle_exit_odm2to1) ++ res = commit_minimal_transition_state(dc, dc->current_state); ++ + context = dc_create_state(dc); + if (!context) + goto context_alloc_fail; +@@ -3872,6 +3893,7 @@ static bool commit_minimal_transition_state(struct dc *dc, + unsigned int i, j; + unsigned int pipe_in_use = 0; + bool subvp_in_use = false; ++ bool odm_in_use = false; + + if (!transition_context) + return false; +@@ -3900,6 +3922,18 @@ static bool commit_minimal_transition_state(struct dc *dc, + } + } + ++ /* If ODM is enabled and we are adding or removing planes from any ODM ++ * pipe, we must use the minimal transition. ++ */ ++ for (i = 0; i < dc->res_pool->pipe_count; i++) { ++ struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; ++ ++ if (pipe->stream && pipe->next_odm_pipe) { ++ odm_in_use = true; ++ break; ++ } ++ } ++ + /* When the OS add a new surface if we have been used all of pipes with odm combine + * and mpc split feature, it need use commit_minimal_transition_state to transition safely. + * After OS exit MPO, it will back to use odm and mpc split with all of pipes, we need +@@ -3908,7 +3942,7 @@ static bool commit_minimal_transition_state(struct dc *dc, + * Reduce the scenarios to use dc_commit_state_no_check in the stage of flip. Especially + * enter/exit MPO when DCN still have enough resources. + */ +- if (pipe_in_use != dc->res_pool->pipe_count && !subvp_in_use) { ++ if (pipe_in_use != dc->res_pool->pipe_count && !subvp_in_use && !odm_in_use) { + dc_release_state(transition_context); + return true; + } +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +index 117d80cb36fb..fe1551393b26 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +@@ -1444,6 +1444,26 @@ static int acquire_first_split_pipe( + split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst; + split_pipe->pipe_idx = i; + ++ split_pipe->stream = stream; ++ return i; ++ } else if (split_pipe->prev_odm_pipe && ++ split_pipe->prev_odm_pipe->plane_state == split_pipe->plane_state) { ++ split_pipe->prev_odm_pipe->next_odm_pipe = split_pipe->next_odm_pipe; ++ if (split_pipe->next_odm_pipe) ++ split_pipe->next_odm_pipe->prev_odm_pipe = split_pipe->prev_odm_pipe; ++ ++ if (split_pipe->prev_odm_pipe->plane_state) ++ resource_build_scaling_params(split_pipe->prev_odm_pipe); ++ ++ memset(split_pipe, 0, sizeof(*split_pipe)); ++ split_pipe->stream_res.tg = pool->timing_generators[i]; ++ split_pipe->plane_res.hubp = pool->hubps[i]; ++ split_pipe->plane_res.ipp = pool->ipps[i]; ++ split_pipe->plane_res.dpp = pool->dpps[i]; ++ split_pipe->stream_res.opp = pool->opps[i]; ++ split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst; ++ split_pipe->pipe_idx = i; ++ + split_pipe->stream = stream; + return i; + } +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-always-switch-off-ODM-before-committ.patch b/patches.suse/drm-amd-display-always-switch-off-ODM-before-committ.patch new file mode 100644 index 0000000..956a62c --- /dev/null +++ b/patches.suse/drm-amd-display-always-switch-off-ODM-before-committ.patch @@ -0,0 +1,52 @@ +From 49a30c3d1a2258fc93cfe6eea8e4951dabadc824 Mon Sep 17 00:00:00 2001 +From: Wenjing Liu +Date: Tue, 15 Aug 2023 10:47:52 -0400 +Subject: [PATCH] drm/amd/display: always switch off ODM before committing more streams +Git-commit: 49a30c3d1a2258fc93cfe6eea8e4951dabadc824 +Alt-commit: ea7e2edca8b2150f945ee25af142fef8438c9944 +Patch-mainline: v6.6-rc1 +References: git-fixes + +ODM power optimization is only supported with single stream. When ODM +power optimization is enabled, we might not have enough free pipes for +enabling other stream. So when we are committing more than 1 stream we +should first switch off ODM power optimization to make room for new +stream and then allocating pipe resource for the new stream. + +Cc: stable@vger.kernel.org +Fixes: 59de751e3845 ("drm/amd/display: add ODM case when looking for first split pipe") +Reviewed-by: Dillon Varone +Acked-by: Hamza Mahfooz +Signed-off-by: Wenjing Liu +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dc/core/dc.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index 54da304b38f0..3a9077b60029 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -2073,12 +2073,12 @@ enum dc_status dc_commit_streams(struct dc *dc, + } + } + +- /* Check for case where we are going from odm 2:1 to max +- * pipe scenario. For these cases, we will call +- * commit_minimal_transition_state() to exit out of odm 2:1 +- * first before processing new streams ++ /* ODM Combine 2:1 power optimization is only applied for single stream ++ * scenario, it uses extra pipes than needed to reduce power consumption ++ * We need to switch off this feature to make room for new streams. + */ +- if (stream_count == dc->res_pool->pipe_count) { ++ if (stream_count > dc->current_state->stream_count && ++ dc->current_state->stream_count == 1) { + for (i = 0; i < dc->res_pool->pipe_count; i++) { + pipe = &dc->current_state->res_ctx.pipe_ctx[i]; + if (pipe->next_odm_pipe) +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-clean-code-style-issues-in-dcn30_set.patch b/patches.suse/drm-amd-display-clean-code-style-issues-in-dcn30_set.patch new file mode 100644 index 0000000..2038638 --- /dev/null +++ b/patches.suse/drm-amd-display-clean-code-style-issues-in-dcn30_set.patch @@ -0,0 +1,100 @@ +From 94369589e4ec13c762fe10a1fdc4463bdfee5d5f Mon Sep 17 00:00:00 2001 +From: Melissa Wen +Date: Tue, 14 Feb 2023 11:14:02 -0100 +Subject: [PATCH] drm/amd/display: clean code-style issues in dcn30_set_mpc_shaper_3dlut +Mime-version: 1.0 +Content-type: text/plain; charset=UTF-8 +Content-transfer-encoding: 8bit +Git-commit: 94369589e4ec13c762fe10a1fdc4463bdfee5d5f +Patch-mainline: v6.3-rc1 +References: git-fixes + +This function has many conditions and all code style issues (identation, +missing braces, etc.) make reading it really annoying. + +Reviewed-by: Christian König +Signed-off-by: Melissa Wen +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + .../drm/amd/display/dc/dcn30/dcn30_hwseq.c | 39 ++++++++++--------- + 1 file changed, 20 insertions(+), 19 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c +index 9ce86f288130..df787fcf8e86 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c +@@ -90,8 +90,8 @@ bool dcn30_set_blend_lut( + return result; + } + +-static bool dcn30_set_mpc_shaper_3dlut( +- struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream) ++static bool dcn30_set_mpc_shaper_3dlut(struct pipe_ctx *pipe_ctx, ++ const struct dc_stream_state *stream) + { + struct dpp *dpp_base = pipe_ctx->plane_res.dpp; + int mpcc_id = pipe_ctx->plane_res.hubp->inst; +@@ -103,19 +103,18 @@ static bool dcn30_set_mpc_shaper_3dlut( + const struct pwl_params *shaper_lut = NULL; + //get the shaper lut params + if (stream->func_shaper) { +- if (stream->func_shaper->type == TF_TYPE_HWPWL) ++ if (stream->func_shaper->type == TF_TYPE_HWPWL) { + shaper_lut = &stream->func_shaper->pwl; +- else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { +- cm_helper_translate_curve_to_hw_format( +- stream->func_shaper, +- &dpp_base->shaper_params, true); ++ } else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { ++ cm_helper_translate_curve_to_hw_format(stream->func_shaper, ++ &dpp_base->shaper_params, true); + shaper_lut = &dpp_base->shaper_params; + } + } + + if (stream->lut3d_func && +- stream->lut3d_func->state.bits.initialized == 1 && +- stream->lut3d_func->state.bits.rmu_idx_valid == 1) { ++ stream->lut3d_func->state.bits.initialized == 1 && ++ stream->lut3d_func->state.bits.rmu_idx_valid == 1) { + if (stream->lut3d_func->state.bits.rmu_mux_num == 0) + mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu0_mux; + else if (stream->lut3d_func->state.bits.rmu_mux_num == 1) +@@ -124,20 +123,22 @@ static bool dcn30_set_mpc_shaper_3dlut( + mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu2_mux; + if (mpcc_id_projected != mpcc_id) + BREAK_TO_DEBUGGER(); +- /*find the reason why logical layer assigned a differant mpcc_id into acquire_post_bldn_3dlut*/ ++ /* find the reason why logical layer assigned a different ++ * mpcc_id into acquire_post_bldn_3dlut ++ */ + acquired_rmu = mpc->funcs->acquire_rmu(mpc, mpcc_id, +- stream->lut3d_func->state.bits.rmu_mux_num); ++ stream->lut3d_func->state.bits.rmu_mux_num); + if (acquired_rmu != stream->lut3d_func->state.bits.rmu_mux_num) + BREAK_TO_DEBUGGER(); +- result = mpc->funcs->program_3dlut(mpc, +- &stream->lut3d_func->lut_3d, +- stream->lut3d_func->state.bits.rmu_mux_num); +- result = mpc->funcs->program_shaper(mpc, shaper_lut, +- stream->lut3d_func->state.bits.rmu_mux_num); +- } else +- /*loop through the available mux and release the requested mpcc_id*/ +- mpc->funcs->release_rmu(mpc, mpcc_id); + ++ result = mpc->funcs->program_3dlut(mpc, &stream->lut3d_func->lut_3d, ++ stream->lut3d_func->state.bits.rmu_mux_num); ++ result = mpc->funcs->program_shaper(mpc, shaper_lut, ++ stream->lut3d_func->state.bits.rmu_mux_num); ++ } else { ++ // loop through the available mux and release the requested mpcc_id ++ mpc->funcs->release_rmu(mpc, mpcc_id); ++ } + + return result; + } +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-dc.h-eliminate-kernel-doc-warnings.patch b/patches.suse/drm-amd-display-dc.h-eliminate-kernel-doc-warnings.patch new file mode 100644 index 0000000..9b422c5 --- /dev/null +++ b/patches.suse/drm-amd-display-dc.h-eliminate-kernel-doc-warnings.patch @@ -0,0 +1,74 @@ +From 57a95e1bd7644b18e31458059256c18b96535f09 Mon Sep 17 00:00:00 2001 +From: Randy Dunlap +Date: Tue, 11 Jul 2023 19:23:38 -0700 +Subject: [PATCH] drm/amd/display: dc.h: eliminate kernel-doc warnings +Mime-version: 1.0 +Content-type: text/plain; charset=UTF-8 +Content-transfer-encoding: 8bit +Git-commit: 57a95e1bd7644b18e31458059256c18b96535f09 +Patch-mainline: v6.6-rc1 +References: git-fixes + +Quash 175 kernel-doc warnings in dc.h by unmarking 2 struct +comments as containing kernel-doc notation and by spelling one +struct field correctly in a kernel-doc comment. + +Fixes: 1682bd1a6b5f ("drm/amd/display: Expand kernel doc for DC") +Fixes: ea76895ffab1 ("drm/amd/display: Document pipe split policy") +Fixes: f6ae69f49fcf ("drm/amd/display: Include surface of unaffected streams") +Reviewed-by: Harry Wentland +Signed-off-by: Randy Dunlap +Signed-off-by: Alex Deucher +Cc: Harry Wentland +Cc: Leo Li +Cc: Rodrigo Siqueira +Cc: Aurabindo Pillai +Cc: Alex Deucher +Cc: amd-gfx@lists.freedesktop.org +Cc: Christian König +Cc: "Pan, Xinhui" +Cc: dri-devel@lists.freedesktop.org +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dc/dc.h | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/gpu/drm/amd/display/dc/dc.h ++++ b/drivers/gpu/drm/amd/display/dc/dc.h +@@ -500,7 +500,7 @@ enum dcn_zstate_support_state { + DCN_ZSTATE_SUPPORT_DISALLOW, + }; + +-/** ++/* + * struct dc_clocks - DC pipe clocks + * + * For any clocks that may differ per pipe only the max is stored in this +@@ -719,7 +719,7 @@ struct dc_state; + struct resource_pool; + struct dce_hwseq; + +-/** ++/* + * struct dc_debug_options - DC debug struct + * + * This struct provides a simple mechanism for developers to change some +@@ -747,7 +747,7 @@ struct dc_debug_options { + bool use_max_lb; + enum dcc_option disable_dcc; + +- /** ++ /* + * @pipe_split_policy: Define which pipe split policy is used by the + * display core. + */ +@@ -1298,7 +1298,7 @@ struct dc_validation_set { + struct dc_stream_state *stream; + + /** +- * @plane_state: Surface state ++ * @plane_states: Surface state + */ + struct dc_plane_state *plane_states[MAX_SURFACES]; + diff --git a/patches.suse/drm-amd-display-ensure-async-flips-are-only-accepted.patch b/patches.suse/drm-amd-display-ensure-async-flips-are-only-accepted.patch new file mode 100644 index 0000000..dcb5d26 --- /dev/null +++ b/patches.suse/drm-amd-display-ensure-async-flips-are-only-accepted.patch @@ -0,0 +1,107 @@ +From a7c0cad0dc060bb77e9c9d235d68441b0fc69507 Mon Sep 17 00:00:00 2001 +From: Hamza Mahfooz +Date: Fri, 4 Aug 2023 11:13:04 -0400 +Subject: [PATCH] drm/amd/display: ensure async flips are only accepted for fast updates +Git-commit: a7c0cad0dc060bb77e9c9d235d68441b0fc69507 +Patch-mainline: v6.6-rc1 +References: git-fixes + +We should be checking to see if async flips are supported in +amdgpu_dm_atomic_check() (i.e. not dm_crtc_helper_atomic_check()). Also, +async flipping isn't supported if a plane's framebuffer changes memory +domains during an atomic commit. So, move the check from +dm_crtc_helper_atomic_check() to amdgpu_dm_atomic_check() and check if +the memory domain has changed in amdgpu_dm_atomic_check(). + +Cc: stable@vger.kernel.org +Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2733 +Fixes: c1e18c44dc7f ("drm/amd/display: only accept async flips for fast updates") +Reviewed-by: Harry Wentland +Signed-off-by: Hamza Mahfooz +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 24 ++++++++++++++++--- + .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 12 ---------- + 2 files changed, 21 insertions(+), 15 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +index dc96417122b7..e3d3af0435ce 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -8082,10 +8082,12 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, + * fast updates. + */ + if (crtc->state->async_flip && +- acrtc_state->update_type != UPDATE_TYPE_FAST) ++ (acrtc_state->update_type != UPDATE_TYPE_FAST || ++ get_mem_type(old_plane_state->fb) != get_mem_type(fb))) + drm_warn_once(state->dev, + "[PLANE:%d:%s] async flip with non-fast update\n", + plane->base.id, plane->name); ++ + bundle->flip_addrs[planes_count].flip_immediate = + crtc->state->async_flip && + acrtc_state->update_type == UPDATE_TYPE_FAST && +@@ -10046,6 +10048,11 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, + + /* Remove exiting planes if they are modified */ + for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { ++ if (old_plane_state->fb && new_plane_state->fb && ++ get_mem_type(old_plane_state->fb) != ++ get_mem_type(new_plane_state->fb)) ++ lock_and_validation_needed = true; ++ + ret = dm_update_plane_state(dc, state, plane, + old_plane_state, + new_plane_state, +@@ -10293,9 +10300,20 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, + struct dm_crtc_state *dm_new_crtc_state = + to_dm_crtc_state(new_crtc_state); + ++ /* ++ * Only allow async flips for fast updates that don't change ++ * the FB pitch, the DCC state, rotation, etc. ++ */ ++ if (new_crtc_state->async_flip && lock_and_validation_needed) { ++ drm_dbg_atomic(crtc->dev, ++ "[CRTC:%d:%s] async flips are only supported for fast updates\n", ++ crtc->base.id, crtc->name); ++ ret = -EINVAL; ++ goto fail; ++ } ++ + dm_new_crtc_state->update_type = lock_and_validation_needed ? +- UPDATE_TYPE_FULL : +- UPDATE_TYPE_FAST; ++ UPDATE_TYPE_FULL : UPDATE_TYPE_FAST; + } + + /* Must be success */ +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +index 30d4c6fd95f5..440fc0869a34 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +@@ -398,18 +398,6 @@ static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc, + return -EINVAL; + } + +- /* +- * Only allow async flips for fast updates that don't change the FB +- * pitch, the DCC state, rotation, etc. +- */ +- if (crtc_state->async_flip && +- dm_crtc_state->update_type != UPDATE_TYPE_FAST) { +- drm_dbg_atomic(crtc->dev, +- "[CRTC:%d:%s] async flips are only supported for fast updates\n", +- crtc->base.id, crtc->name); +- return -EINVAL; +- } +- + /* In some use cases, like reset, no stream is attached */ + if (!dm_crtc_state->stream) + return 0; +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-fix-ABM-disablement.patch b/patches.suse/drm-amd-display-fix-ABM-disablement.patch new file mode 100644 index 0000000..2f93a54 --- /dev/null +++ b/patches.suse/drm-amd-display-fix-ABM-disablement.patch @@ -0,0 +1,62 @@ +From b9f46f0b98784e40288ee393f863f553fde062fa Mon Sep 17 00:00:00 2001 +From: Hamza Mahfooz +Date: Wed, 22 Nov 2023 14:50:34 -0500 +Subject: [PATCH] drm/amd/display: fix ABM disablement +Git-commit: b9f46f0b98784e40288ee393f863f553fde062fa +Patch-mainline: v6.7-rc4 +References: git-fixes + +On recent versions of DMUB firmware, if we want to completely disable +ABM we have to pass ABM_LEVEL_IMMEDIATE_DISABLE as the requested ABM +level to DMUB. Otherwise, LCD eDP displays are unable to reach their +maximum brightness levels. So, to fix this whenever the user requests an +ABM level of 0 pass ABM_LEVEL_IMMEDIATE_DISABLE to DMUB instead. Also, +to keep the user's experience consistent map ABM_LEVEL_IMMEDIATE_DISABLE +to 0 when a user tries to read the requested ABM level. + +Cc: stable@vger.kernel.org # 6.1+ +Reviewed-by: Harry Wentland +Signed-off-by: Hamza Mahfooz +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +index ee97814ebd99..b452796fc6d3 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -6267,7 +6267,7 @@ int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, + dm_new_state->underscan_enable = val; + ret = 0; + } else if (property == adev->mode_info.abm_level_property) { +- dm_new_state->abm_level = val; ++ dm_new_state->abm_level = val ?: ABM_LEVEL_IMMEDIATE_DISABLE; + ret = 0; + } + +@@ -6312,7 +6312,8 @@ int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, + *val = dm_state->underscan_enable; + ret = 0; + } else if (property == adev->mode_info.abm_level_property) { +- *val = dm_state->abm_level; ++ *val = (dm_state->abm_level != ABM_LEVEL_IMMEDIATE_DISABLE) ? ++ dm_state->abm_level : 0; + ret = 0; + } + +@@ -6385,7 +6386,8 @@ void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) + state->pbn = 0; + + if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) +- state->abm_level = amdgpu_dm_abm_level; ++ state->abm_level = amdgpu_dm_abm_level ?: ++ ABM_LEVEL_IMMEDIATE_DISABLE; + + __drm_atomic_helper_connector_reset(connector, &state->base); + } +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-fix-a-NULL-pointer-dereference-in-am.patch b/patches.suse/drm-amd-display-fix-a-NULL-pointer-dereference-in-am.patch new file mode 100644 index 0000000..f6a0e39 --- /dev/null +++ b/patches.suse/drm-amd-display-fix-a-NULL-pointer-dereference-in-am.patch @@ -0,0 +1,45 @@ +From b71f4ade1b8900d30c661d6c27f87c35214c398c Mon Sep 17 00:00:00 2001 +From: Mario Limonciello +Date: Wed, 8 Nov 2023 13:31:57 -0600 +Subject: [PATCH] drm/amd/display: fix a NULL pointer dereference in amdgpu_dm_i2c_xfer() +Git-commit: b71f4ade1b8900d30c661d6c27f87c35214c398c +Patch-mainline: v6.7-rc2 +References: git-fixes + +When ddc_service_construct() is called, it explicitly checks both the +link type and whether there is something on the link which will +dictate whether the pin is marked as hw_supported. + +If the pin isn't set or the link is not set (such as from +unloading/reloading amdgpu in an IGT test) then fail the +amdgpu_dm_i2c_xfer() call. + +Cc: stable@vger.kernel.org +Fixes: 22676bc500c2 ("drm/amd/display: Fix dmub soft hang for PSR 1") +Link: https://github.com/fwupd/fwupd/issues/6327 +Signed-off-by: Mario Limonciello +Reviewed-by: Harry Wentland +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +index 6f99f6754c11..5ec7acf65ee1 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -7481,6 +7481,9 @@ static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, + int i; + int result = -EIO; + ++ if (!ddc_service->ddc_pin || !ddc_service->ddc_pin->hw_info.hw_supported) ++ return result; ++ + cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL); + + if (!cmd.payloads) +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-fix-dc-core-dc.c-kernel-doc.patch b/patches.suse/drm-amd-display-fix-dc-core-dc.c-kernel-doc.patch new file mode 100644 index 0000000..71d3977 --- /dev/null +++ b/patches.suse/drm-amd-display-fix-dc-core-dc.c-kernel-doc.patch @@ -0,0 +1,163 @@ +From db4107e92a817502ad19fdd30250f87dcb6f6331 Mon Sep 17 00:00:00 2001 +From: Randy Dunlap +Date: Wed, 28 Dec 2022 17:00:51 -0800 +Subject: [PATCH] drm/amd/display: fix dc/core/dc.c kernel-doc +Mime-version: 1.0 +Content-type: text/plain; charset=UTF-8 +Content-transfer-encoding: 8bit +Git-commit: db4107e92a817502ad19fdd30250f87dcb6f6331 +Patch-mainline: v6.3-rc1 +References: git-fixes + +Fix all kernel-doc warnings in dc/core/dc.c: + +dc.c:385: warning: missing initial short description on line: + * dc_stream_adjust_vmin_vmax: +dc.c:392: warning: contents before sections +dc.c:399: warning: No description found for return value of 'dc_stream_adjust_vmin_vmax' +dc.c:434: warning: Excess function parameter 'adjust' description in 'dc_stream_get_last_used_drr_vtotal' +dc.c:434: warning: No description found for return value of 'dc_stream_get_last_used_drr_vtotal' +dc.c:574: warning: No description found for return value of 'dc_stream_configure_crc' +dc.c:1746: warning: No description found for return value of 'dc_commit_state_no_check' +dc.c:4991: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst + * dc_extended_blank_supported 0 Decide whether extended blank is supported +dc.c:4991: warning: missing initial short description on line: + * dc_extended_blank_supported 0 Decide whether extended blank is supported +dc.c:4723: warning: Function parameter or member 'dc' not described in 'dc_enable_dmub_outbox' +dc.c:4926: warning: Function parameter or member 'dc' not described in 'dc_process_dmub_dpia_hpd_int_enable' +dc.c:4926: warning: Function parameter or member 'hpd_int_enable' not described in 'dc_process_dmub_dpia_hpd_int_enable' +12 warnings + +Signed-off-by: Randy Dunlap +Reported-by: kernel test robot +Cc: Rodrigo Siqueira +Cc: Alex Deucher +Cc: Hamza Mahfooz +Cc: Harry Wentland +Cc: Leo Li +Cc: Christian König +Cc: "Pan, Xinhui" +Cc: amd-gfx@lists.freedesktop.org +Signed-off-by: Hamza Mahfooz +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dc/core/dc.c | 40 +++++++++++++++++++------------ + 1 file changed, 25 insertions(+), 15 deletions(-) + +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -382,16 +382,18 @@ static void dc_perf_trace_destroy(struct + } + + /** +- * dc_stream_adjust_vmin_vmax: ++ * dc_stream_adjust_vmin_vmax - look up pipe context & update parts of DRR ++ * @dc: dc reference ++ * @stream: Initial dc stream state ++ * @adjust: Updated parameters for vertical_total_min and vertical_total_max + * + * Looks up the pipe context of dc_stream_state and updates the + * vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh + * Rate, which is a power-saving feature that targets reducing panel + * refresh rate while the screen is static + * +- * @dc: dc reference +- * @stream: Initial dc stream state +- * @adjust: Updated parameters for vertical_total_min and vertical_total_max ++ * Return: %true if the pipe context is found and adjusted; ++ * %false if the pipe context is not found. + */ + bool dc_stream_adjust_vmin_vmax(struct dc *dc, + struct dc_stream_state *stream, +@@ -427,14 +429,17 @@ bool dc_stream_adjust_vmin_vmax(struct d + } + + /** +- * dc_stream_get_last_used_drr_vtotal - dc_stream_get_last_vrr_vtotal ++ * dc_stream_get_last_used_drr_vtotal - Looks up the pipe context of ++ * dc_stream_state and gets the last VTOTAL used by DRR (Dynamic Refresh Rate) + * + * @dc: [in] dc reference + * @stream: [in] Initial dc stream state +- * @adjust: [in] Updated parameters for vertical_total_min and ++ * @refresh_rate: [in] new refresh_rate + * +- * Looks up the pipe context of dc_stream_state and gets the last VTOTAL used +- * by DRR (Dynamic Refresh Rate) ++ * Return: %true if the pipe context is found and there is an associated ++ * timing_generator for the DC; ++ * %false if the pipe context is not found or there is no ++ * timing_generator for the DC. + */ + bool dc_stream_get_last_used_drr_vtotal(struct dc *dc, + struct dc_stream_state *stream, +@@ -581,7 +586,10 @@ bool dc_stream_stop_dmcu_crc_win_update( + * once. + * + * By default, only CRC0 is configured, and the entire frame is used to +- * calculate the crc. ++ * calculate the CRC. ++ * ++ * Return: %false if the stream is not found or CRC capture is not supported; ++ * %true if the stream has been configured. + */ + bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream, + struct crc_params *crc_window, bool enable, bool continuous) +@@ -650,7 +658,7 @@ bool dc_stream_configure_crc(struct dc * + * dc_stream_configure_crc needs to be called beforehand to enable CRCs. + * + * Return: +- * false if stream is not found, or if CRCs are not enabled. ++ * %false if stream is not found, or if CRCs are not enabled. + */ + bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream, + uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb) +@@ -1755,6 +1763,8 @@ void dc_z10_save_init(struct dc *dc) + /* + * Applies given context to HW and copy it into current context. + * It's up to the user to release the src context afterwards. ++ * ++ * Return: an enum dc_status result code for the operation + */ + static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context) + { +@@ -4652,7 +4662,7 @@ bool dc_enable_dmub_notifications(struct + /** + * dc_enable_dmub_outbox - Enables DMUB unsolicited notification + * +- * dc: [in] dc structure ++ * @dc: [in] dc structure + * + * Enables DMUB unsolicited notifications to x86 via outbox. + */ +@@ -4853,8 +4863,8 @@ enum dc_status dc_process_dmub_set_mst_s + /** + * dc_process_dmub_dpia_hpd_int_enable - Submits DPIA DPD interruption + * +- * @dc [in]: dc structure +- * @hpd_int_enable [in]: 1 for hpd int enable, 0 to disable ++ * @dc: [in] dc structure ++ * @hpd_int_enable: [in] 1 for hpd int enable, 0 to disable + * + * Submits dpia hpd int enable command to dmub via inbox message + */ +@@ -4935,7 +4945,7 @@ void dc_notify_vsync_int_state(struct dc + } + + /** +- * dc_extended_blank_supported 0 Decide whether extended blank is supported ++ * dc_extended_blank_supported - Decide whether extended blank is supported + * + * @dc: [in] Current DC state + * +@@ -4944,7 +4954,7 @@ void dc_notify_vsync_int_state(struct dc + * ability to enter z9/z10. + * + * Return: +- * Indicate whether extended blank is supported (true or false) ++ * Indicate whether extended blank is supported (%true or %false) + */ + bool dc_extended_blank_supported(struct dc *dc) + { diff --git a/patches.suse/drm-amd-display-fix-hw-rotated-modes-when-PSR-SU-is-.patch b/patches.suse/drm-amd-display-fix-hw-rotated-modes-when-PSR-SU-is-.patch new file mode 100644 index 0000000..07f76f8 --- /dev/null +++ b/patches.suse/drm-amd-display-fix-hw-rotated-modes-when-PSR-SU-is-.patch @@ -0,0 +1,86 @@ +From f528ee145bd0076cd0ed7e7b2d435893e6329e98 Mon Sep 17 00:00:00 2001 +From: Hamza Mahfooz +Date: Tue, 5 Dec 2023 14:55:04 -0500 +Subject: [PATCH] drm/amd/display: fix hw rotated modes when PSR-SU is enabled +Git-commit: f528ee145bd0076cd0ed7e7b2d435893e6329e98 +Alt-commit: 0497ae6f8830816d9277a8d5c8d9bf5966f292e1 +Patch-mainline: v6.7-rc6 +References: git-fixes + +We currently don't support dirty rectangles on hardware rotated modes. +So, if a user is using hardware rotated modes with PSR-SU enabled, +use PSR-SU FFU for all rotated planes (including cursor planes). + +Cc: stable@vger.kernel.org +Fixes: 30ebe41582d1 ("drm/amd/display: add FB_DAMAGE_CLIPS support") +Reported-by: Kai-Heng Feng +Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/2952 +Tested-by: Kai-Heng Feng +Tested-by: Bin Li +Reviewed-by: Mario Limonciello +Signed-off-by: Hamza Mahfooz +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++ + drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 1 + + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 ++- + drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 12 ++++++++++-- + 4 files changed, 16 insertions(+), 3 deletions(-) + +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -4968,6 +4968,9 @@ static void fill_dc_dirty_rects(struct d + if (plane->type == DRM_PLANE_TYPE_CURSOR) + return; + ++ if (new_plane_state->rotation != DRM_MODE_ROTATE_0) ++ goto ffu; ++ + num_clips = drm_plane_get_damage_clips_count(new_plane_state); + clips = drm_plane_get_damage_clips(new_plane_state); + +--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h ++++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +@@ -465,6 +465,7 @@ struct dc_cursor_mi_param { + struct fixed31_32 v_scale_ratio; + enum dc_rotation_angle rotation; + bool mirror; ++ struct dc_stream_state *stream; + }; + + /* IPP related types */ +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -3433,7 +3433,8 @@ void dcn10_set_cursor_position(struct pi + .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz, + .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert, + .rotation = pipe_ctx->plane_state->rotation, +- .mirror = pipe_ctx->plane_state->horizontal_mirror ++ .mirror = pipe_ctx->plane_state->horizontal_mirror, ++ .stream = pipe_ctx->stream, + }; + bool pipe_split_on = false; + bool odm_combine_on = (pipe_ctx->next_odm_pipe != NULL) || +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c +@@ -1075,8 +1075,16 @@ void hubp2_cursor_set_position( + if (src_y_offset < 0) + src_y_offset = 0; + /* Save necessary cursor info x, y position. w, h is saved in attribute func. */ +- hubp->cur_rect.x = src_x_offset + param->viewport.x; +- hubp->cur_rect.y = src_y_offset + param->viewport.y; ++ if (param->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && ++ param->rotation != ROTATION_ANGLE_0) { ++ hubp->cur_rect.x = 0; ++ hubp->cur_rect.y = 0; ++ hubp->cur_rect.w = param->stream->timing.h_addressable; ++ hubp->cur_rect.h = param->stream->timing.v_addressable; ++ } else { ++ hubp->cur_rect.x = src_x_offset + param->viewport.x; ++ hubp->cur_rect.y = src_y_offset + param->viewport.y; ++ } + } + + void hubp2_clk_cntl(struct hubp *hubp, bool enable) diff --git a/patches.suse/drm-amd-display-fix-kernel-doc-issues-in-dc.h.patch b/patches.suse/drm-amd-display-fix-kernel-doc-issues-in-dc.h.patch new file mode 100644 index 0000000..3f28c45 --- /dev/null +++ b/patches.suse/drm-amd-display-fix-kernel-doc-issues-in-dc.h.patch @@ -0,0 +1,79 @@ +From ef8d147fd4425b1c46ad8f2df567632b6c5897e1 Mon Sep 17 00:00:00 2001 +From: Randy Dunlap +Date: Thu, 17 Nov 2022 09:20:09 -0800 +Subject: [PATCH] drm/amd/display: fix kernel-doc issues in dc.h +Git-commit: ef8d147fd4425b1c46ad8f2df567632b6c5897e1 +Patch-mainline: v6.2-rc1 +References: git-fixes + +Fix these kernel-doc complaints: + +drivers/gpu/drm/amd/display/dc/dc.h:505: warning: cannot understand function prototype: 'struct dc_clocks ' +dc.h:472: warning: Enum value 'MPC_SPLIT_AVOID' not described in enum 'pipe_split_policy' +dc.h:472: warning: Enum value 'MPC_SPLIT_AVOID_MULT_DISP' not described in enum 'pipe_split_policy' +dc.h:532: warning: Incorrect use of kernel-doc format: * @fw_based_mclk_switching + +Fixes: ea76895ffab1 ("drm/amd/display: Document pipe split policy") +Fixes: 1682bd1a6b5f ("drm/amd/display: Expand kernel doc for DC") +Signed-off-by: Randy Dunlap +Cc: Rodrigo Siqueira +Cc: Alex Deucher +Cc: Harry Wentland +Cc: Leo Li +Cc: amd-gfx@lists.freedesktop.org +Cc: David Airlie +Cc: Daniel Vetter +Cc: dri-devel@lists.freedesktop.org +Reviewed-by: Harry Wentland +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dc/dc.h | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h +index b02d1f3d3e7c..57fc9193c770 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc.h ++++ b/drivers/gpu/drm/amd/display/dc/dc.h +@@ -458,15 +458,15 @@ enum pipe_split_policy { + MPC_SPLIT_DYNAMIC = 0, + + /** +- * @MPC_SPLIT_DYNAMIC: Avoid pipe split, which means that DC will not ++ * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not + * try any sort of split optimization. + */ + MPC_SPLIT_AVOID = 1, + + /** +- * @MPC_SPLIT_DYNAMIC: With this option, DC will only try to optimize +- * the pipe utilization when using a single display; if the user +- * connects to a second display, DC will avoid pipe split. ++ * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to ++ * optimize the pipe utilization when using a single display; if the ++ * user connects to a second display, DC will avoid pipe split. + */ + MPC_SPLIT_AVOID_MULT_DISP = 2, + }; +@@ -497,7 +497,7 @@ enum dcn_zstate_support_state { + }; + + /** +- * dc_clocks - DC pipe clocks ++ * struct dc_clocks - DC pipe clocks + * + * For any clocks that may differ per pipe only the max is stored in this + * structure +@@ -528,7 +528,7 @@ struct dc_clocks { + bool fclk_prev_p_state_change_support; + int num_ways; + +- /** ++ /* + * @fw_based_mclk_switching + * + * DC has a mechanism that leverage the variable refresh rate to switch +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-fix-unbounded-requesting-for-high-pi.patch b/patches.suse/drm-amd-display-fix-unbounded-requesting-for-high-pi.patch new file mode 100644 index 0000000..988d839 --- /dev/null +++ b/patches.suse/drm-amd-display-fix-unbounded-requesting-for-high-pi.patch @@ -0,0 +1,57 @@ +From 655435df0936ce2fda0d5ced7e50101179a3acfd Mon Sep 17 00:00:00 2001 +From: Dmytro Laktyushkin +Date: Tue, 1 Nov 2022 17:09:11 -0400 +Subject: [PATCH] drm/amd/display: fix unbounded requesting for high pixel rate modes on dcn315 +Git-commit: 655435df0936ce2fda0d5ced7e50101179a3acfd +Patch-mainline: v6.2-rc1 +References: git-fixes + +Unbounded requesting is getting configured for odm mode calculations which +is incorrect. This change checks whether mode requires odm ahead of time. + +Reviewed-by: Jun Lei +Acked-by: Tom Chung +Signed-off-by: Dmytro Laktyushkin +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c | 4 +++- + drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 5 +++++ + drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h | 1 + + 3 files changed, 9 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c +@@ -1707,7 +1707,9 @@ static int dcn315_populate_dml_pipes_fro + dc->config.enable_4to1MPC = true; + context->bw_ctx.dml.ip.det_buffer_size_kbytes = + (max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB / 4) * DCN3_15_CRB_SEGMENT_SIZE_KB; +- } else if (!is_dual_plane(pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120) { ++ } else if (!is_dual_plane(pipe->plane_state->format) ++ && pipe->plane_state->src_rect.width <= 5120 ++ && pipe->stream->timing.pix_clk_100hz < dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)) { + /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */ + context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; + pipes[0].pipe.src.unbounded_req_mode = true; +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c +@@ -807,3 +807,8 @@ void dcn316_update_bw_bounding_box(struc + else + dml_init_instance(&dc->dml, &dcn3_16_soc, &dcn3_16_ip, DML_PROJECT_DCN31_FPGA); + } ++ ++int dcn_get_max_non_odm_pix_rate_100hz(struct _vcs_dpi_soc_bounding_box_st *soc) ++{ ++ return soc->clock_limits[0].dispclk_mhz * 10000.0 / (1.0 + soc->dcn_downspread_percent / 100.0); ++} +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h +@@ -46,5 +46,6 @@ void dcn31_calculate_wm_and_dlg_fp( + void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params); + void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params); + void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params); ++int dcn_get_max_non_odm_pix_rate_100hz(struct _vcs_dpi_soc_bounding_box_st *soc); + + #endif /* __DCN31_FPU_H__*/ diff --git a/patches.suse/drm-amd-display-perform-a-bounds-check-before-fillin.patch b/patches.suse/drm-amd-display-perform-a-bounds-check-before-fillin.patch new file mode 100644 index 0000000..bc62bc6 --- /dev/null +++ b/patches.suse/drm-amd-display-perform-a-bounds-check-before-fillin.patch @@ -0,0 +1,72 @@ +From af22d6a869cc26b519bfdcd54293c53f2e491870 Mon Sep 17 00:00:00 2001 +From: Hamza Mahfooz +Date: Wed, 21 Jun 2023 15:19:05 -0400 +Subject: [PATCH] drm/amd/display: perform a bounds check before filling dirty rectangles +Git-commit: af22d6a869cc26b519bfdcd54293c53f2e491870 +Patch-mainline: v6.5-rc1 +References: git-fixes + +Currently, it is possible for us to access memory that we shouldn't. +Since, we acquire (possibly dangling) pointers to dirty rectangles +before doing a bounds check to make sure we can actually accommodate the +number of dirty rectangles userspace has requested to fill. This issue +is especially evident if a compositor requests both MPO and damage clips +at the same time, in which case I have observed a soft-hang. So, to +avoid this issue, perform the bounds check before filling a single dirty +rectangle and WARN() about it, if it is ever attempted in +fill_dc_dirty_rect(). + +Cc: stable@vger.kernel.org # 6.1+ +Fixes: 30ebe41582d1 ("drm/amd/display: add FB_DAMAGE_CLIPS support") +Reviewed-by: Leo Li +Signed-off-by: Hamza Mahfooz +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 ++++--------- + 1 file changed, 4 insertions(+), 9 deletions(-) + +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -4907,11 +4907,7 @@ static inline void fill_dc_dirty_rect(st + int32_t y, int32_t width, int32_t height, + int *i, bool ffu) + { +- if (*i > DC_MAX_DIRTY_RECTS) +- return; +- +- if (*i == DC_MAX_DIRTY_RECTS) +- goto out; ++ WARN_ON(*i >= DC_MAX_DIRTY_RECTS); + + dirty_rect->x = x; + dirty_rect->y = y; +@@ -4927,7 +4923,6 @@ static inline void fill_dc_dirty_rect(st + "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)", + plane->base.id, x, y, width, height); + +-out: + (*i)++; + } + +@@ -5009,6 +5004,9 @@ static void fill_dc_dirty_rects(struct d + new_plane_state->plane->base.id, + bb_changed, fb_changed, num_clips); + ++ if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS) ++ goto ffu; ++ + if (bb_changed) { + fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], + new_plane_state->crtc_x, +@@ -5038,9 +5036,6 @@ static void fill_dc_dirty_rects(struct d + new_plane_state->crtc_h, &i, false); + } + +- if (i > DC_MAX_DIRTY_RECTS) +- goto ffu; +- + flip_addrs->dirty_rect_count = i; + return; + diff --git a/patches.suse/drm-amd-display-set-per-pipe-dppclk-to-0-when-dpp-is.patch b/patches.suse/drm-amd-display-set-per-pipe-dppclk-to-0-when-dpp-is.patch new file mode 100644 index 0000000..63e2354 --- /dev/null +++ b/patches.suse/drm-amd-display-set-per-pipe-dppclk-to-0-when-dpp-is.patch @@ -0,0 +1,92 @@ +From 6609141c49df1b86fbad26a8643d4b4044f28b11 Mon Sep 17 00:00:00 2001 +From: Dmytro Laktyushkin +Date: Tue, 22 Nov 2022 10:06:19 -0500 +Subject: [PATCH] drm/amd/display: set per pipe dppclk to 0 when dpp is off +Git-commit: 6609141c49df1b86fbad26a8643d4b4044f28b11 +Patch-mainline: v6.2-rc1 +References: git-fixes + +The 'commit 52e4fdf09ebc ("drm/amd/display: use low clocks for no plane +configs")' introduced a change that set low clock values for DCN31 and +DCN32. As a result of these changes, DC started to spam the log with the +following warning: + +Acked-by: Takashi Iwai + +------------[ cut here ]------------ +WARNING: CPU: 8 PID: 1486 at +drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dccg.c:58 +dccg2_update_dpp_dto+0x3f/0xf0 [amdgpu] +[..] +CPU: 8 PID: 1486 Comm: kms_atomic Tainted: G W 5.18.0+ #1 +RIP: 0010:dccg2_update_dpp_dto+0x3f/0xf0 [amdgpu] +RSP: 0018:ffffbbd8025334d0 EFLAGS: 00010206 +RAX: 00000000000001ee RBX: ffffa02c87dd3de0 RCX: 00000000000a7f80 +RDX: 000000000007dec3 RSI: 0000000000000000 RDI: ffffa02c87dd3de0 +RBP: ffffbbd8025334e8 R08: 0000000000000001 R09: 0000000000000005 +R10: 00000000000331a0 R11: ffffffffc0b03d80 R12: ffffa02ca576d000 +R13: ffffa02cd02c0000 R14: 00000000001453bc R15: ffffa02cdc280000 +[..] +dcn20_update_clocks_update_dpp_dto+0x4e/0xa0 [amdgpu] +dcn32_update_clocks+0x5d9/0x650 [amdgpu] +dcn20_prepare_bandwidth+0x49/0x100 [amdgpu] +dcn30_prepare_bandwidth+0x63/0x80 [amdgpu] +dc_commit_state_no_check+0x39d/0x13e0 [amdgpu] +dc_commit_streams+0x1f9/0x3b0 [amdgpu] +dc_commit_state+0x37/0x120 [amdgpu] +amdgpu_dm_atomic_commit_tail+0x5e5/0x2520 [amdgpu] +? _raw_spin_unlock_irqrestore+0x1f/0x40 +? down_trylock+0x2c/0x40 +? vprintk_emit+0x186/0x2c0 +? vprintk_default+0x1d/0x20 +? vprintk+0x4e/0x60 + +We can easily trigger this issue by using a 4k@120 or a 2k@165 and +running some of the kms_atomic tests. This warning is triggered because +the per-pipe clock update is not happening; this commit fixes this issue +by ensuring that DPPCLK is updated when calculating the watermark and +dlg is invoked. + +Fixes: 2641c7b78081 ("drm/amd/display: use low clocks for no plane configs") +Reported-by: Mark Broadworth +Reviewed-by: Rodrigo Siqueira +Signed-off-by: Dmytro Laktyushkin +Signed-off-by: Alex Deucher +--- + drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 3 +++ + drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 5 ++++- + 2 files changed, 7 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c +index 12b23bd50e19..b37d14369a62 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c +@@ -559,6 +559,9 @@ void dcn31_calculate_wm_and_dlg_fp( + context->bw_ctx.bw.dcn.clk.dramclk_khz = 0; + context->bw_ctx.bw.dcn.clk.fclk_khz = 0; + context->bw_ctx.bw.dcn.clk.p_state_change_support = true; ++ for (i = 0; i < dc->res_pool->pipe_count; i++) ++ if (context->res_ctx.pipe_ctx[i].stream) ++ context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 0; + } + } + +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +index 3a9b714e7138..ac324ce11597 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +@@ -1320,7 +1320,10 @@ static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, + + if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) + context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; +- context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; ++ if (context->res_ctx.pipe_ctx[i].plane_state) ++ context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; ++ else ++ context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 0; + context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; + pipe_idx++; + } +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-update-extended-blank-for-dcn314-onw.patch b/patches.suse/drm-amd-display-update-extended-blank-for-dcn314-onw.patch new file mode 100644 index 0000000..ac38d77 --- /dev/null +++ b/patches.suse/drm-amd-display-update-extended-blank-for-dcn314-onw.patch @@ -0,0 +1,287 @@ +From 469a62938a45ef382c9cb7b9fec6c6c1fcd781c0 Mon Sep 17 00:00:00 2001 +From: Gabe Teeger +Date: Thu, 6 Apr 2023 17:03:06 -0400 +Subject: [PATCH] drm/amd/display: update extended blank for dcn314 onwards +Git-commit: 469a62938a45ef382c9cb7b9fec6c6c1fcd781c0 +Patch-mainline: v6.5-rc1 +References: git-fixes + +[Why] +Flickering and underflow was observed when testing extended +blank on dcn314. + +[What] +Vstartup is contrainted by vblank_nom, so adjusting it to include +non-adjusted vtotal in its calculation during freesync video +means that Vstartup is not changed when vtotal changes. +This fixed the flickering + underflow. + +dc_extended_blank_supported function was removed +because extended blank is only relevant to when +zstate is supported. The increased vtotal during +freesync can be passed to dml regardless of whether +extended blank is supported or not, so this function is +not needed. + +Updates were made recently in dml to the calculation of +min_dst_y_next_start. Dml input for dcn314 will now +always use the newer calculation for min_dst_y_next_start. +Dml input for older dcn versions remains untouched. + +The variable optimized_min_dst_y_next_start +is replaced everywhere with min_dst_y_next_start, +and the updated dml allows min_dst_y_next_start to +increase to an optimized value during freesync video, +then return to default when freesync is disengaged. + +Also removed registry key for controlling +extended blank feature. + +Tested-by: Daniel Wheeler +Reviewed-by: Nicholas Kazlauskas +Acked-by: Rodrigo Siqueira +Signed-off-by: Gabe Teeger +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/display/dc/core/dc.c | 21 ----------------- + drivers/gpu/drm/amd/display/dc/dc.h | 2 -- + .../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 4 ++-- + .../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 23 +++++++++---------- + .../dc/dml/dcn31/display_rq_dlg_calc_31.c | 3 +-- + .../amd/display/dc/dml/dcn314/dcn314_fpu.c | 14 +++++++---- + .../dc/dml/dcn314/display_rq_dlg_calc_314.c | 16 ++++--------- + .../amd/display/dc/dml/display_mode_structs.h | 3 +-- + 8 files changed, 29 insertions(+), 57 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index c10243ef93b6..89a245e3c9ac 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -2607,9 +2607,6 @@ static enum surface_update_type check_update_surfaces_for_stream( + stream_update->vrr_active_variable)) + su_flags->bits.fams_changed = 1; + +- if (stream_update->crtc_timing_adjust && dc_extended_blank_supported(dc)) +- su_flags->bits.crtc_timing_adjust = 1; +- + if (su_flags->raw != 0) + overall_type = UPDATE_TYPE_FULL; + +@@ -4849,21 +4846,3 @@ void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bo + if (pipe->stream_res.abm && pipe->stream_res.abm->funcs->set_abm_pause) + pipe->stream_res.abm->funcs->set_abm_pause(pipe->stream_res.abm, !enable, i, pipe->stream_res.tg->inst); + } +- +-/** +- * dc_extended_blank_supported - Decide whether extended blank is supported +- * +- * @dc: [in] Current DC state +- * +- * Extended blank is a freesync optimization feature to be enabled in the +- * future. During the extra vblank period gained from freesync, we have the +- * ability to enter z9/z10. +- * +- * Return: +- * Indicate whether extended blank is supported (%true or %false) +- */ +-bool dc_extended_blank_supported(struct dc *dc) +-{ +- return dc->debug.extended_blank_optimization && !dc->debug.disable_z10 +- && dc->caps.zstate_support && dc->caps.is_apu; +-} +diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h +index dc0a61ca99d0..5268d98b96dc 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc.h ++++ b/drivers/gpu/drm/amd/display/dc/dc.h +@@ -2128,8 +2128,6 @@ struct dc_sink_init_data { + bool converter_disable_audio; + }; + +-bool dc_extended_blank_supported(struct dc *dc); +- + struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); + + /* Newer interfaces */ +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +index 5800acf6aae1..f49c1c0d6274 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +@@ -2130,7 +2130,7 @@ void dcn20_optimize_bandwidth( + dc->clk_mgr, + context, + true); +- if (dc_extended_blank_supported(dc) && context->bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW) { ++ if (context->bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW) { + for (i = 0; i < dc->res_pool->pipe_count; ++i) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + +@@ -2138,7 +2138,7 @@ void dcn20_optimize_bandwidth( + && pipe_ctx->stream->adjust.v_total_min == pipe_ctx->stream->adjust.v_total_max + && pipe_ctx->stream->adjust.v_total_max > pipe_ctx->stream->timing.v_total) + pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp, +- pipe_ctx->dlg_regs.optimized_min_dst_y_next_start); ++ pipe_ctx->dlg_regs.min_dst_y_next_start); + } + } + } +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +index f1c1a4b5fcac..7661f8946aa3 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +@@ -948,10 +948,10 @@ static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struc + { + int plane_count; + int i; +- unsigned int optimized_min_dst_y_next_start_us; ++ unsigned int min_dst_y_next_start_us; + + plane_count = 0; +- optimized_min_dst_y_next_start_us = 0; ++ min_dst_y_next_start_us = 0; + for (i = 0; i < dc->res_pool->pipe_count; i++) { + if (context->res_ctx.pipe_ctx[i].plane_state) + plane_count++; +@@ -973,19 +973,18 @@ static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struc + else if (context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) { + struct dc_link *link = context->streams[0]->sink->link; + struct dc_stream_status *stream_status = &context->stream_status[0]; ++ struct dc_stream_state *current_stream = context->streams[0]; + int minmum_z8_residency = dc->debug.minimum_z8_residency_time > 0 ? dc->debug.minimum_z8_residency_time : 1000; + bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency; + bool is_pwrseq0 = link->link_index == 0; ++ bool isFreesyncVideo; + +- if (dc_extended_blank_supported(dc)) { +- for (i = 0; i < dc->res_pool->pipe_count; i++) { +- if (context->res_ctx.pipe_ctx[i].stream == context->streams[0] +- && context->res_ctx.pipe_ctx[i].stream->adjust.v_total_min == context->res_ctx.pipe_ctx[i].stream->adjust.v_total_max +- && context->res_ctx.pipe_ctx[i].stream->adjust.v_total_min > context->res_ctx.pipe_ctx[i].stream->timing.v_total) { +- optimized_min_dst_y_next_start_us = +- context->res_ctx.pipe_ctx[i].dlg_regs.optimized_min_dst_y_next_start_us; +- break; +- } ++ isFreesyncVideo = current_stream->adjust.v_total_min == current_stream->adjust.v_total_max; ++ isFreesyncVideo = isFreesyncVideo && current_stream->timing.v_total < current_stream->adjust.v_total_min; ++ for (i = 0; i < dc->res_pool->pipe_count; i++) { ++ if (context->res_ctx.pipe_ctx[i].stream == current_stream && isFreesyncVideo) { ++ min_dst_y_next_start_us = context->res_ctx.pipe_ctx[i].dlg_regs.min_dst_y_next_start_us; ++ break; + } + } + +@@ -993,7 +992,7 @@ static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struc + if (stream_status->plane_count > 1) + return DCN_ZSTATE_SUPPORT_DISALLOW; + +- if (is_pwrseq0 && (context->bw_ctx.dml.vba.StutterPeriod > 5000.0 || optimized_min_dst_y_next_start_us > 5000)) ++ if (is_pwrseq0 && (context->bw_ctx.dml.vba.StutterPeriod > 5000.0 || min_dst_y_next_start_us > 5000)) + return DCN_ZSTATE_SUPPORT_ALLOW; + else if (is_pwrseq0 && link->psr_settings.psr_version == DC_PSR_VERSION_1 && !link->panel_config.psr.disable_psr) + return allow_z8 ? DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY : DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY; +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c +index 2244e4fb8c96..fcde8f21b8be 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c +@@ -987,8 +987,7 @@ static void dml_rq_dlg_get_dlg_params( + + dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start; + disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start) * dml_pow(2, 2)); +- disp_dlg_regs->optimized_min_dst_y_next_start_us = 0; +- disp_dlg_regs->optimized_min_dst_y_next_start = disp_dlg_regs->min_dst_y_next_start; ++ disp_dlg_regs->min_dst_y_next_start_us = 0; + ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18)); + + dml_print("DML_DLG: %s: min_ttu_vblank (us) = %3.2f\n", __func__, min_ttu_vblank); +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c +index 44082f65de1f..19370b872a91 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c +@@ -286,6 +286,7 @@ int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *c + struct resource_context *res_ctx = &context->res_ctx; + struct pipe_ctx *pipe; + bool upscaled = false; ++ bool isFreesyncVideo = false; + + dc_assert_fp_enabled(); + +@@ -299,9 +300,16 @@ int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *c + pipe = &res_ctx->pipe_ctx[i]; + timing = &pipe->stream->timing; + +- if (dc_extended_blank_supported(dc) && pipe->stream->adjust.v_total_max == pipe->stream->adjust.v_total_min +- && pipe->stream->adjust.v_total_min > timing->v_total) ++ isFreesyncVideo = pipe->stream->adjust.v_total_max == pipe->stream->adjust.v_total_min; ++ isFreesyncVideo = isFreesyncVideo && pipe->stream->adjust.v_total_min > timing->v_total; ++ ++ if (!isFreesyncVideo) { ++ pipes[pipe_cnt].pipe.dest.vblank_nom = ++ dcn3_14_ip.VBlankNomDefaultUS / (timing->h_total / (timing->pix_clk_100hz / 10000.0)); ++ } else { + pipes[pipe_cnt].pipe.dest.vtotal = pipe->stream->adjust.v_total_min; ++ pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; ++ } + + if (pipe->plane_state && + (pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height || +@@ -323,8 +331,6 @@ int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *c + pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; + pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; + pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; +- pipes[pipe_cnt].pipe.dest.vblank_nom = +- dcn3_14_ip.VBlankNomDefaultUS / (timing->h_total / (timing->pix_clk_100hz / 10000.0)); + pipes[pipe_cnt].pipe.src.dcc_rate = 3; + pipes[pipe_cnt].dout.dsc_input_bpc = 0; + +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c +index ea4eb66066c4..4f945458b2b7 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c +@@ -1051,7 +1051,6 @@ static void dml_rq_dlg_get_dlg_params( + + float vba__refcyc_per_req_delivery_pre_l = get_refcyc_per_req_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + float vba__refcyc_per_req_delivery_l = get_refcyc_per_req_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA +- int blank_lines = 0; + + memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs)); + memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs)); +@@ -1075,17 +1074,10 @@ static void dml_rq_dlg_get_dlg_params( + min_ttu_vblank = get_min_ttu_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA + + dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start; +- disp_dlg_regs->optimized_min_dst_y_next_start = disp_dlg_regs->min_dst_y_next_start; +- disp_dlg_regs->optimized_min_dst_y_next_start_us = 0; +- disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start) * dml_pow(2, 2)); +- blank_lines = (dst->vblank_end + dst->vtotal_min - dst->vblank_start - dst->vstartup_start - 1); +- if (blank_lines < 0) +- blank_lines = 0; +- if (blank_lines != 0) { +- disp_dlg_regs->optimized_min_dst_y_next_start = vba__min_dst_y_next_start; +- disp_dlg_regs->optimized_min_dst_y_next_start_us = (disp_dlg_regs->optimized_min_dst_y_next_start * dst->hactive) / (unsigned int) dst->pixel_rate_mhz; +- disp_dlg_regs->min_dst_y_next_start = disp_dlg_regs->optimized_min_dst_y_next_start; +- } ++ disp_dlg_regs->min_dst_y_next_start_us = ++ (vba__min_dst_y_next_start * dst->hactive) / (unsigned int) dst->pixel_rate_mhz; ++ disp_dlg_regs->min_dst_y_next_start = vba__min_dst_y_next_start * dml_pow(2, 2); ++ + ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18)); + + dml_print("DML_DLG: %s: min_ttu_vblank (us) = %3.2f\n", __func__, min_ttu_vblank); +diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h +index 3c077164f362..ff0246a9458f 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h ++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h +@@ -619,8 +619,7 @@ struct _vcs_dpi_display_dlg_regs_st { + unsigned int refcyc_h_blank_end; + unsigned int dlg_vblank_end; + unsigned int min_dst_y_next_start; +- unsigned int optimized_min_dst_y_next_start; +- unsigned int optimized_min_dst_y_next_start_us; ++ unsigned int min_dst_y_next_start_us; + unsigned int refcyc_per_htotal; + unsigned int refcyc_x_after_scaler; + unsigned int dst_y_after_scaler; +-- +2.43.0 + diff --git a/patches.suse/drm-amd-display-use-low-clocks-for-no-plane-configs.patch b/patches.suse/drm-amd-display-use-low-clocks-for-no-plane-configs.patch new file mode 100644 index 0000000..a519adf --- /dev/null +++ b/patches.suse/drm-amd-display-use-low-clocks-for-no-plane-configs.patch @@ -0,0 +1,109 @@ +From 2641c7b7808191cba25ba28b82bb73ca294924cc Mon Sep 17 00:00:00 2001 +From: Dmytro Laktyushkin +Date: Fri, 7 Oct 2022 11:01:08 -0400 +Subject: [PATCH] drm/amd/display: use low clocks for no plane configs +Git-commit: 2641c7b7808191cba25ba28b82bb73ca294924cc +Patch-mainline: v6.2-rc1 +References: git-fixes + +Stream only configurations do not require DCFCLK, SOCCLK, DPPCLK +or FCLK. They also always allow pstate change. + +Reviewed-by: Charlene Liu +Acked-by: Tom Chung +Signed-off-by: Dmytro Laktyushkin +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + .../drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 18 ++++++++++++++---- + .../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 14 +++++++++++++- + 2 files changed, 27 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c +index 7dd0845d1bd9..4cdad8674b8e 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c +@@ -483,7 +483,7 @@ void dcn31_calculate_wm_and_dlg_fp( + int pipe_cnt, + int vlevel) + { +- int i, pipe_idx, active_dpp_count = 0; ++ int i, pipe_idx, active_hubp_count = 0; + double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; + + dc_assert_fp_enabled(); +@@ -529,7 +529,7 @@ void dcn31_calculate_wm_and_dlg_fp( + continue; + + if (context->res_ctx.pipe_ctx[i].plane_state) +- active_dpp_count++; ++ active_hubp_count++; + + pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt); + pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); +@@ -547,9 +547,19 @@ void dcn31_calculate_wm_and_dlg_fp( + } + + dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); +- /* For 31x apu pstate change is only supported if possible in vactive or if there are no active dpps */ ++ /* For 31x apu pstate change is only supported if possible in vactive*/ + context->bw_ctx.bw.dcn.clk.p_state_change_support = +- context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_dram_clock_change_vactive || !active_dpp_count; ++ context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_dram_clock_change_vactive; ++ /* If DCN isn't making memory requests we can allow pstate change and lower clocks */ ++ if (!active_hubp_count) { ++ context->bw_ctx.bw.dcn.clk.socclk_khz = 0; ++ context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; ++ context->bw_ctx.bw.dcn.clk.dcfclk_khz = 0; ++ context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = 0; ++ context->bw_ctx.bw.dcn.clk.dramclk_khz = 0; ++ context->bw_ctx.bw.dcn.clk.fclk_khz = 0; ++ context->bw_ctx.bw.dcn.clk.p_state_change_support = true; ++ } + } + + void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +index 853ffb704985..dadaac249836 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +@@ -1228,7 +1228,7 @@ static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, + display_e2e_pipe_params_st *pipes, + int pipe_cnt, int vlevel) + { +- int i, pipe_idx; ++ int i, pipe_idx, active_hubp_count = 0; + bool usr_retraining_support = false; + bool unbounded_req_enabled = false; + +@@ -1273,6 +1273,8 @@ static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, + for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { + if (!context->res_ctx.pipe_ctx[i].stream) + continue; ++ if (context->res_ctx.pipe_ctx[i].plane_state) ++ active_hubp_count++; + pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, + pipe_idx); + pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, +@@ -1298,6 +1300,16 @@ static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, + context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; + pipe_idx++; + } ++ /* If DCN isn't making memory requests we can allow pstate change and lower clocks */ ++ if (!active_hubp_count) { ++ context->bw_ctx.bw.dcn.clk.socclk_khz = 0; ++ context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; ++ context->bw_ctx.bw.dcn.clk.dcfclk_khz = 0; ++ context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = 0; ++ context->bw_ctx.bw.dcn.clk.dramclk_khz = 0; ++ context->bw_ctx.bw.dcn.clk.fclk_khz = 0; ++ context->bw_ctx.bw.dcn.clk.p_state_change_support = true; ++ } + /*save a original dppclock copy*/ + context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; + context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; +-- +2.43.0 + diff --git a/patches.suse/drm-amd-pm-Fix-error-of-MACO-flag-setting-code.patch b/patches.suse/drm-amd-pm-Fix-error-of-MACO-flag-setting-code.patch new file mode 100644 index 0000000..fa554dc --- /dev/null +++ b/patches.suse/drm-amd-pm-Fix-error-of-MACO-flag-setting-code.patch @@ -0,0 +1,60 @@ +From 7f3e6b840fa8b0889d776639310a5dc672c1e9e1 Mon Sep 17 00:00:00 2001 +From: Ma Jun +Date: Tue, 31 Oct 2023 11:11:04 +0800 +Subject: [PATCH] drm/amd/pm: Fix error of MACO flag setting code +Git-commit: 7f3e6b840fa8b0889d776639310a5dc672c1e9e1 +Patch-mainline: v6.7-rc1 +References: git-fixes + +MACO only works if BACO is supported + +Signed-off-by: Ma Jun +Reviewed-by: Kenneth Feng +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org # 6.1.x +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 8 ++++---- + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 9 +++++---- + 2 files changed, 9 insertions(+), 8 deletions(-) + +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +@@ -324,12 +324,12 @@ static int smu_v13_0_0_check_powerplay_t + if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_HARDWAREDC) + smu->dc_controlled_by_gpio = true; + +- if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_BACO || +- powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO) ++ if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_BACO) { + smu_baco->platform_support = true; + +- if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO) +- smu_baco->maco_support = true; ++ if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO) ++ smu_baco->maco_support = true; ++ } + + table_context->thermal_controller_type = + powerplay_table->thermal_controller_type; +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +@@ -326,12 +326,13 @@ static int smu_v13_0_7_check_powerplay_t + if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_HARDWAREDC) + smu->dc_controlled_by_gpio = true; + +- if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_BACO || +- powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_MACO) ++ if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_BACO) { + smu_baco->platform_support = true; + +- if (smu_baco->platform_support && (BoardTable->HsrEnabled || BoardTable->VddqOffEnabled)) +- smu_baco->maco_support = true; ++ if ((powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_MACO) ++ && (BoardTable->HsrEnabled || BoardTable->VddqOffEnabled)) ++ smu_baco->maco_support = true; ++ } + + table_context->thermal_controller_type = + powerplay_table->thermal_controller_type; diff --git a/patches.suse/drm-amd-pm-fix-a-memleak-in-aldebaran_tables_init.patch b/patches.suse/drm-amd-pm-fix-a-memleak-in-aldebaran_tables_init.patch new file mode 100644 index 0000000..324f90f --- /dev/null +++ b/patches.suse/drm-amd-pm-fix-a-memleak-in-aldebaran_tables_init.patch @@ -0,0 +1,40 @@ +From 7a88f23e768491bae653b444a96091d2aaeb0818 Mon Sep 17 00:00:00 2001 +From: Dinghao Liu +Date: Thu, 23 Nov 2023 15:33:22 +0800 +Subject: [PATCH] drm/amd/pm: fix a memleak in aldebaran_tables_init +Git-commit: 7a88f23e768491bae653b444a96091d2aaeb0818 +Patch-mainline: v6.7-rc4 +References: git-fixes + +When kzalloc() for smu_table->ecc_table fails, we should free +the previously allocated resources to prevent memleak. + +Fixes: edd794208555 ("drm/amd/pm: add message smu to get ecc_table v2") +Signed-off-by: Dinghao Liu +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c +index 1a6675d70a4b..f1440869d1ce 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c +@@ -257,8 +257,11 @@ static int aldebaran_tables_init(struct smu_context *smu) + } + + smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL); +- if (!smu_table->ecc_table) ++ if (!smu_table->ecc_table) { ++ kfree(smu_table->metrics_table); ++ kfree(smu_table->gpu_metrics_table); + return -ENOMEM; ++ } + + return 0; + } +-- +2.43.0 + diff --git a/patches.suse/drm-amd-smu-use-AverageGfxclkFrequency-to-replace-pr.patch b/patches.suse/drm-amd-smu-use-AverageGfxclkFrequency-to-replace-pr.patch new file mode 100644 index 0000000..8d43ac1 --- /dev/null +++ b/patches.suse/drm-amd-smu-use-AverageGfxclkFrequency-to-replace-pr.patch @@ -0,0 +1,36 @@ +From 4a37c55b859a69f429bfa7fab4fc43ee470b60ed Mon Sep 17 00:00:00 2001 +From: Jane Jian +Date: Thu, 20 Jul 2023 18:08:07 +0800 +Subject: [PATCH] drm/amd/smu: use AverageGfxclkFrequency* to replace previous GFX Curr Clock +Git-commit: 4a37c55b859a69f429bfa7fab4fc43ee470b60ed +Patch-mainline: v6.5-rc4 +References: git-fixes + +Report current GFX clock also from average clock value as the original +CurrClock data is not valid/accurate any more as per FW team + +Signed-off-by: Jane Jian +Reviewed-by: Lijo Lazar +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +index b9bde5fa8f8f..3d188616ba24 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +@@ -1734,7 +1734,7 @@ static ssize_t smu_v13_0_0_get_gpu_metrics(struct smu_context *smu, + gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency; + gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency; + +- gpu_metrics->current_gfxclk = metrics->CurrClock[PPCLK_GFXCLK]; ++ gpu_metrics->current_gfxclk = gpu_metrics->average_gfxclk_frequency; + gpu_metrics->current_socclk = metrics->CurrClock[PPCLK_SOCCLK]; + gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK]; + gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0]; +-- +2.43.0 + diff --git a/patches.suse/drm-amdgpu-Force-order-between-a-read-and-write-to-t.patch b/patches.suse/drm-amdgpu-Force-order-between-a-read-and-write-to-t.patch new file mode 100644 index 0000000..2fff4d1 --- /dev/null +++ b/patches.suse/drm-amdgpu-Force-order-between-a-read-and-write-to-t.patch @@ -0,0 +1,58 @@ +From 4b27a33c3b173bef1d19ba89e0b9b812b4fddd25 Mon Sep 17 00:00:00 2001 +From: Alex Sierra +Date: Mon, 20 Nov 2023 11:31:32 -0600 +Subject: [PATCH] drm/amdgpu: Force order between a read and write to the same address +Git-commit: 4b27a33c3b173bef1d19ba89e0b9b812b4fddd25 +Patch-mainline: v6.7-rc4 +References: git-fixes + +Setting register to force ordering to prevent read/write or write/read +hazards for un-cached modes. + +Signed-off-by: Alex Sierra +Acked-by: Alex Deucher +Reviewed-by: Felix Kuehling +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org # 6.1.x +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 8 ++++++++ + drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h | 2 ++ + 2 files changed, 10 insertions(+) + +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +@@ -82,6 +82,10 @@ MODULE_FIRMWARE("amdgpu/gc_11_0_4_me.bin + MODULE_FIRMWARE("amdgpu/gc_11_0_4_mec.bin"); + MODULE_FIRMWARE("amdgpu/gc_11_0_4_rlc.bin"); + ++static const struct soc15_reg_golden golden_settings_gc_11_0[] = { ++ SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x20000000, 0x20000000) ++}; ++ + static const struct soc15_reg_golden golden_settings_gc_11_0_1[] = + { + SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010), +@@ -274,6 +278,10 @@ static void gfx_v11_0_init_golden_regist + default: + break; + } ++ soc15_program_register_sequence(adev, ++ golden_settings_gc_11_0, ++ (const u32)ARRAY_SIZE(golden_settings_gc_11_0)); ++ + } + + static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, +--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h +@@ -6369,6 +6369,8 @@ + #define regTCP_INVALIDATE_BASE_IDX 1 + #define regTCP_STATUS 0x19a1 + #define regTCP_STATUS_BASE_IDX 1 ++#define regTCP_CNTL 0x19a2 ++#define regTCP_CNTL_BASE_IDX 1 + #define regTCP_CNTL2 0x19a3 + #define regTCP_CNTL2_BASE_IDX 1 + #define regTCP_DEBUG_INDEX 0x19a5 diff --git a/patches.suse/drm-amdgpu-Match-against-exact-bootloader-status.patch b/patches.suse/drm-amdgpu-Match-against-exact-bootloader-status.patch new file mode 100644 index 0000000..abff5ad --- /dev/null +++ b/patches.suse/drm-amdgpu-Match-against-exact-bootloader-status.patch @@ -0,0 +1,53 @@ +From d3de41ee5febe5c2d9989fe9810bce2bb54a3a8e Mon Sep 17 00:00:00 2001 +From: Lijo Lazar +Date: Tue, 25 Jul 2023 19:11:54 +0530 +Subject: [PATCH] drm/amdgpu: Match against exact bootloader status +Git-commit: d3de41ee5febe5c2d9989fe9810bce2bb54a3a8e +Patch-mainline: v6.5-rc6 +References: git-fixes + +On PSP v13.x ASICs, boot loader will set only the MSB to 1 and clear the +least significant bits for any command submission. Hence match against +the exact register value, otherwise a register value of all 0xFFs also +could falsely indicate that boot loader is ready. Also, from PSP v13.0.6 +and newer, bits[7:0] will be used to indicate command error status. + +Signed-off-by: Lijo Lazar +Acked-by: Alex Deucher +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 15 ++++++++------- + 1 file changed, 8 insertions(+), 7 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c +index e1a392bcea70..af5685f4cb34 100644 +--- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c +@@ -137,14 +137,15 @@ static int psp_v13_0_wait_for_bootloader(struct psp_context *psp) + int ret; + int retry_loop; + ++ /* Wait for bootloader to signify that it is ready having bit 31 of ++ * C2PMSG_35 set to 1. All other bits are expected to be cleared. ++ * If there is an error in processing command, bits[7:0] will be set. ++ * This is applicable for PSP v13.0.6 and newer. ++ */ + for (retry_loop = 0; retry_loop < 10; retry_loop++) { +- /* Wait for bootloader to signify that is +- ready having bit 31 of C2PMSG_35 set to 1 */ +- ret = psp_wait_for(psp, +- SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), +- 0x80000000, +- 0x80000000, +- false); ++ ret = psp_wait_for( ++ psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), ++ 0x80000000, 0xffffffff, false); + + if (ret == 0) + return 0; +-- +2.43.0 + diff --git a/patches.suse/drm-amdgpu-Unset-context-priority-is-now-invalid.patch b/patches.suse/drm-amdgpu-Unset-context-priority-is-now-invalid.patch new file mode 100644 index 0000000..d7738c9 --- /dev/null +++ b/patches.suse/drm-amdgpu-Unset-context-priority-is-now-invalid.patch @@ -0,0 +1,50 @@ +From eab0261967aeab528db4d0a51806df8209aec179 Mon Sep 17 00:00:00 2001 +From: Luben Tuikov +Date: Mon, 16 Oct 2023 22:24:39 -0400 +Subject: [PATCH] drm/amdgpu: Unset context priority is now invalid +Mime-version: 1.0 +Content-type: text/plain; charset=UTF-8 +Content-transfer-encoding: 8bit +Git-commit: eab0261967aeab528db4d0a51806df8209aec179 +Patch-mainline: v6.6-rc7 +References: git-fixes + +A context priority value of AMD_CTX_PRIORITY_UNSET is now invalid--instead of +carrying it around and passing it to the Direct Rendering Manager--and it +becomes AMD_CTX_PRIORITY_NORMAL in amdgpu_ctx_ioctl(), the gateway to context +creation. + +Cc: Alex Deucher +Cc: Christian König +Signed-off-by: Luben Tuikov +Acked-by: Alex Deucher +Link: https://lore.kernel.org/r/20231017035656.8211-1-luben.tuikov@amd.com +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +index 0dc9c655c4fb..092962b93064 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +@@ -47,7 +47,6 @@ const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM] = { + bool amdgpu_ctx_priority_is_valid(int32_t ctx_prio) + { + switch (ctx_prio) { +- case AMDGPU_CTX_PRIORITY_UNSET: + case AMDGPU_CTX_PRIORITY_VERY_LOW: + case AMDGPU_CTX_PRIORITY_LOW: + case AMDGPU_CTX_PRIORITY_NORMAL: +@@ -55,6 +54,7 @@ bool amdgpu_ctx_priority_is_valid(int32_t ctx_prio) + case AMDGPU_CTX_PRIORITY_VERY_HIGH: + return true; + default: ++ case AMDGPU_CTX_PRIORITY_UNSET: + return false; + } + } +-- +2.43.0 + diff --git a/patches.suse/drm-amdgpu-Update-min-to-min_t-in-amdgpu_info_ioctl.patch b/patches.suse/drm-amdgpu-Update-min-to-min_t-in-amdgpu_info_ioctl.patch new file mode 100644 index 0000000..94e2341 --- /dev/null +++ b/patches.suse/drm-amdgpu-Update-min-to-min_t-in-amdgpu_info_ioctl.patch @@ -0,0 +1,88 @@ +From a0cc8e1512ad72c9f97cdcb76d42715730adaf62 Mon Sep 17 00:00:00 2001 +From: Srinivasan Shanmugam +Date: Sun, 23 Jul 2023 12:29:14 +0530 +Subject: [PATCH] drm/amdgpu: Update min() to min_t() in 'amdgpu_info_ioctl' +Mime-version: 1.0 +Content-type: text/plain; charset=UTF-8 +Content-transfer-encoding: 8bit +Git-commit: a0cc8e1512ad72c9f97cdcb76d42715730adaf62 +Patch-mainline: v6.6-rc1 +References: git-fixes + +Fixes the following: + +Warning: min() should probably be min_t(size_t, size, sizeof(ip)) ++ ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip))); + +And other style fixes: + +Warning: Prefer 'unsigned int' to bare use of 'unsigned' +Warning: Missing a blank line after declarations + +Cc: Christian König +Cc: Alex Deucher +Signed-off-by: Srinivasan Shanmugam +Reviewed-by: Alex Deucher +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 14 ++++++++------ + 1 file changed, 8 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +index 12f3c7ad7d04..631c5ab3f7dc 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +@@ -557,6 +557,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) + crtc = (struct drm_crtc *)minfo->crtcs[i]; + if (crtc && crtc->base.id == info->mode_crtc.id) { + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); ++ + ui32 = amdgpu_crtc->crtc_id; + found = 1; + break; +@@ -575,7 +576,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) + if (ret) + return ret; + +- ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip))); ++ ret = copy_to_user(out, &ip, min_t(size_t, size, sizeof(ip))); + return ret ? -EFAULT : 0; + } + case AMDGPU_INFO_HW_IP_COUNT: { +@@ -721,17 +722,18 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) + ? -EFAULT : 0; + } + case AMDGPU_INFO_READ_MMR_REG: { +- unsigned n, alloc_size; ++ unsigned int n, alloc_size; + uint32_t *regs; +- unsigned se_num = (info->read_mmr_reg.instance >> ++ unsigned int se_num = (info->read_mmr_reg.instance >> + AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & + AMDGPU_INFO_MMR_SE_INDEX_MASK; +- unsigned sh_num = (info->read_mmr_reg.instance >> ++ unsigned int sh_num = (info->read_mmr_reg.instance >> + AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & + AMDGPU_INFO_MMR_SH_INDEX_MASK; + + /* set full masks if the userspace set all bits +- * in the bitfields */ ++ * in the bitfields ++ */ + if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) + se_num = 0xffffffff; + else if (se_num >= AMDGPU_GFX_MAX_SE) +@@ -896,7 +898,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) + return ret; + } + case AMDGPU_INFO_VCE_CLOCK_TABLE: { +- unsigned i; ++ unsigned int i; + struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; + struct amd_vce_state *vce_state; + +-- +2.43.0 + diff --git a/patches.suse/drm-amdgpu-lower-CS-errors-to-debug-severity.patch b/patches.suse/drm-amdgpu-lower-CS-errors-to-debug-severity.patch new file mode 100644 index 0000000..acde749 --- /dev/null +++ b/patches.suse/drm-amdgpu-lower-CS-errors-to-debug-severity.patch @@ -0,0 +1,39 @@ +From 17daf01ab4e3e5a5929747aa05cc15eb2bad5438 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= +Date: Thu, 9 Nov 2023 10:14:14 +0100 +Subject: [PATCH] drm/amdgpu: lower CS errors to debug severity +Mime-version: 1.0 +Content-type: text/plain; charset=UTF-8 +Content-transfer-encoding: 8bit +Git-commit: 17daf01ab4e3e5a5929747aa05cc15eb2bad5438 +Patch-mainline: v6.7-rc1 +References: git-fixes + +Otherwise userspace can spam the logs by using incorrect input values. + +Signed-off-by: Christian König +Reviewed-by: Alex Deucher +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +index 0245de81cabd..1e35e9c06b09 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +@@ -1414,7 +1414,7 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) + if (r == -ENOMEM) + DRM_ERROR("Not enough memory for command submission!\n"); + else if (r != -ERESTARTSYS && r != -EAGAIN) +- DRM_ERROR("Failed to process the buffer list %d!\n", r); ++ DRM_DEBUG("Failed to process the buffer list %d!\n", r); + goto error_fini; + } + +-- +2.43.0 + diff --git a/patches.suse/drm-amdgpu-pm-make-gfxclock-consistent-for-sienna-ci.patch b/patches.suse/drm-amdgpu-pm-make-gfxclock-consistent-for-sienna-ci.patch new file mode 100644 index 0000000..eb2b26b --- /dev/null +++ b/patches.suse/drm-amdgpu-pm-make-gfxclock-consistent-for-sienna-ci.patch @@ -0,0 +1,45 @@ +From a4eb11824170d742531998f4ebd1c6a18b63db47 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Tue, 13 Jun 2023 12:15:38 -0400 +Subject: [PATCH] drm/amdgpu/pm: make gfxclock consistent for sienna cichlid +Git-commit: a4eb11824170d742531998f4ebd1c6a18b63db47 +Patch-mainline: v6.5-rc3 +References: git-fixes + +Use average gfxclock for consistency with other dGPUs. + +Reviewed-by: Kenneth Feng +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org # 6.1.x +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 8 ++++++-- + 1 file changed, 6 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +index f6599c00a6fd..0cda3b276f61 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +@@ -1927,12 +1927,16 @@ static int sienna_cichlid_read_sensor(struct smu_context *smu, + *size = 4; + break; + case AMDGPU_PP_SENSOR_GFX_MCLK: +- ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); ++ ret = sienna_cichlid_get_smu_metrics_data(smu, ++ METRICS_CURR_UCLK, ++ (uint32_t *)data); + *(uint32_t *)data *= 100; + *size = 4; + break; + case AMDGPU_PP_SENSOR_GFX_SCLK: +- ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data); ++ ret = sienna_cichlid_get_smu_metrics_data(smu, ++ METRICS_AVERAGE_GFXCLK, ++ (uint32_t *)data); + *(uint32_t *)data *= 100; + *size = 4; + break; +-- +2.43.0 + diff --git a/patches.suse/drm-amdgpu-pm-make-mclk-consistent-for-smu-13.0.7.patch b/patches.suse/drm-amdgpu-pm-make-mclk-consistent-for-smu-13.0.7.patch new file mode 100644 index 0000000..4e951ff --- /dev/null +++ b/patches.suse/drm-amdgpu-pm-make-mclk-consistent-for-smu-13.0.7.patch @@ -0,0 +1,35 @@ +From 068c8bb10f37bb84824625dbbda053a3a3e0d6e1 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Tue, 13 Jun 2023 12:36:17 -0400 +Subject: [PATCH] drm/amdgpu/pm: make mclk consistent for smu 13.0.7 +Git-commit: 068c8bb10f37bb84824625dbbda053a3a3e0d6e1 +Patch-mainline: v6.5-rc3 +References: git-fixes + +Use current uclk to be consistent with other dGPUs. + +Reviewed-by: Kenneth Feng +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org # 6.1.x +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +index 3ba02131e682..b1f0937ccade 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +@@ -949,7 +949,7 @@ static int smu_v13_0_7_read_sensor(struct smu_context *smu, + break; + case AMDGPU_PP_SENSOR_GFX_MCLK: + ret = smu_v13_0_7_get_smu_metrics_data(smu, +- METRICS_AVERAGE_UCLK, ++ METRICS_CURR_UCLK, + (uint32_t *)data); + *(uint32_t *)data *= 100; + *size = 4; +-- +2.43.0 + diff --git a/patches.suse/drm-amdgpu-smu13-drop-compute-workload-workaround.patch b/patches.suse/drm-amdgpu-smu13-drop-compute-workload-workaround.patch new file mode 100644 index 0000000..86261c8 --- /dev/null +++ b/patches.suse/drm-amdgpu-smu13-drop-compute-workload-workaround.patch @@ -0,0 +1,68 @@ +From 23170863ea0a0965d224342c0eb2ad8303b1f267 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Wed, 1 Nov 2023 15:48:14 -0400 +Subject: [PATCH] drm/amdgpu/smu13: drop compute workload workaround +Git-commit: 23170863ea0a0965d224342c0eb2ad8303b1f267 +Patch-mainline: v6.7-rc1 +References: git-fixes + +This was fixed in PMFW before launch and is no longer +required. + +Reviewed-by: Yang Wang +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org # 6.1.x +Acked-by: Takashi Iwai + +--- + .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 32 ++----------------- + 1 file changed, 2 insertions(+), 30 deletions(-) + +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +index ef0c30075658..82c4e1f1c6f0 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +@@ -2530,38 +2530,10 @@ static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu, + } + } + +- if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE && +- (((smu->adev->pdev->device == 0x744C) && (smu->adev->pdev->revision == 0xC8)) || +- ((smu->adev->pdev->device == 0x744C) && (smu->adev->pdev->revision == 0xCC)))) { +- ret = smu_cmn_update_table(smu, +- SMU_TABLE_ACTIVITY_MONITOR_COEFF, +- WORKLOAD_PPLIB_COMPUTE_BIT, +- (void *)(&activity_monitor_external), +- false); +- if (ret) { +- dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); +- return ret; +- } +- +- ret = smu_cmn_update_table(smu, +- SMU_TABLE_ACTIVITY_MONITOR_COEFF, +- WORKLOAD_PPLIB_CUSTOM_BIT, +- (void *)(&activity_monitor_external), +- true); +- if (ret) { +- dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); +- return ret; +- } +- +- workload_type = smu_cmn_to_asic_specific_index(smu, +- CMN2ASIC_MAPPING_WORKLOAD, +- PP_SMC_POWER_PROFILE_CUSTOM); +- } else { +- /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ +- workload_type = smu_cmn_to_asic_specific_index(smu, ++ /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ ++ workload_type = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_WORKLOAD, + smu->power_profile_mode); +- } + + if (workload_type < 0) + return -EINVAL; +-- +2.43.0 + diff --git a/patches.suse/drm-bridge-tc358762-Instruct-DSI-host-to-generate-HS.patch b/patches.suse/drm-bridge-tc358762-Instruct-DSI-host-to-generate-HS.patch new file mode 100644 index 0000000..7813cc3 --- /dev/null +++ b/patches.suse/drm-bridge-tc358762-Instruct-DSI-host-to-generate-HS.patch @@ -0,0 +1,38 @@ +From 362fa8f6e6a05089872809f4465bab9d011d05b3 Mon Sep 17 00:00:00 2001 +From: Marek Vasut +Date: Thu, 15 Jun 2023 22:19:00 +0200 +Subject: [PATCH] drm/bridge: tc358762: Instruct DSI host to generate HSE packets +Git-commit: 362fa8f6e6a05089872809f4465bab9d011d05b3 +Patch-mainline: v6.6-rc1 +References: git-fixes + +This bridge seems to need the HSE packet, otherwise the image is +shifted up and corrupted at the bottom. This makes the bridge +work with Samsung DSIM on i.MX8MM and i.MX8MP. + +Signed-off-by: Marek Vasut +Reviewed-by: Sam Ravnborg +Signed-off-by: Robert Foss +Link: https://patchwork.freedesktop.org/patch/msgid/20230615201902.566182-3-marex@denx.de +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/bridge/tc358762.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/bridge/tc358762.c b/drivers/gpu/drm/bridge/tc358762.c +index 5e00c08b9954..77f2ec9de9e5 100644 +--- a/drivers/gpu/drm/bridge/tc358762.c ++++ b/drivers/gpu/drm/bridge/tc358762.c +@@ -241,7 +241,7 @@ static int tc358762_probe(struct mipi_dsi_device *dsi) + dsi->lanes = 1; + dsi->format = MIPI_DSI_FMT_RGB888; + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | +- MIPI_DSI_MODE_LPM; ++ MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_VIDEO_HSE; + + ret = tc358762_parse_dt(ctx); + if (ret < 0) +-- +2.43.0 + diff --git a/patches.suse/drm-edid-Add-quirk-for-OSVR-HDK-2.0.patch b/patches.suse/drm-edid-Add-quirk-for-OSVR-HDK-2.0.patch new file mode 100644 index 0000000..79cfa31 --- /dev/null +++ b/patches.suse/drm-edid-Add-quirk-for-OSVR-HDK-2.0.patch @@ -0,0 +1,40 @@ +From 98d4cb705bc00afd4a9a71cc1e84f7111682639a Mon Sep 17 00:00:00 2001 +From: Ralph Campbell +Date: Tue, 20 Jun 2023 23:19:03 -0700 +Subject: [PATCH] drm/edid: Add quirk for OSVR HDK 2.0 +Git-commit: 98d4cb705bc00afd4a9a71cc1e84f7111682639a +Patch-mainline: v6.6-rc1 +References: git-fixes + +The OSVR virtual reality headset HDK 2.0 uses a different EDID +vendor and device identifier than the HDK 1.1 - 1.4 headsets. +Add the HDK 2.0 vendor and device identifier to the quirks table so +that window managers do not try to display the desktop screen on the +headset display. + +Closes: https://gitlab.freedesktop.org/drm/misc/-/issues/30 +Signed-off-by: Ralph Campbell +Tested-by: Ralph Campbell +Signed-off-by: Jani Nikula +Link: https://patchwork.freedesktop.org/patch/msgid/20230621061903.3422648-1-rcampbell@nvidia.com +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/drm_edid.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c +index 39b13417b749..f95152fac427 100644 +--- a/drivers/gpu/drm/drm_edid.c ++++ b/drivers/gpu/drm/drm_edid.c +@@ -230,6 +230,7 @@ static const struct edid_quirk { + + /* OSVR HDK and HDK2 VR Headsets */ + EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP), ++ EDID_QUIRK('A', 'U', 'O', 0x1111, EDID_QUIRK_NON_DESKTOP), + }; + + /* +-- +2.43.0 + diff --git a/patches.suse/drm-exynos-fix-a-possible-null-pointer-dereference-d.patch b/patches.suse/drm-exynos-fix-a-possible-null-pointer-dereference-d.patch new file mode 100644 index 0000000..6eca973 --- /dev/null +++ b/patches.suse/drm-exynos-fix-a-possible-null-pointer-dereference-d.patch @@ -0,0 +1,61 @@ +From 2e63972a2de14482d0eae1a03a73e379f1c3f44c Mon Sep 17 00:00:00 2001 +From: Tuo Li +Date: Fri, 30 Jun 2023 10:19:06 +0800 +Subject: [PATCH] drm/exynos: fix a possible null-pointer dereference due to data race in exynos_drm_crtc_atomic_disable() +Git-commit: 2e63972a2de14482d0eae1a03a73e379f1c3f44c +Patch-mainline: v6.6-rc1 +References: git-fixes + +The variable crtc->state->event is often protected by the lock +crtc->dev->event_lock when is accessed. However, it is accessed as a +condition of an if statement in exynos_drm_crtc_atomic_disable() without +holding the lock: + + if (crtc->state->event && !crtc->state->active) + +However, if crtc->state->event is changed to NULL by another thread right +after the conditions of the if statement is checked to be true, a +null-pointer dereference can occur in drm_crtc_send_vblank_event(): + + e->pipe = pipe; + +To fix this possible null-pointer dereference caused by data race, the +spin lock coverage is extended to protect the if statement as well as the +function call to drm_crtc_send_vblank_event(). + +Reported-by: BassCheck +Link: https://sites.google.com/view/basscheck/home +Signed-off-by: Tuo Li +Reviewed-by: Krzysztof Kozlowski +Added relevant link. + +Signed-off-by: Inki Dae +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/exynos/exynos_drm_crtc.c | 5 ++--- + 1 file changed, 2 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c b/drivers/gpu/drm/exynos/exynos_drm_crtc.c +index 4153f302de7c..d19e796c2061 100644 +--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c ++++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c +@@ -39,13 +39,12 @@ static void exynos_drm_crtc_atomic_disable(struct drm_crtc *crtc, + if (exynos_crtc->ops->atomic_disable) + exynos_crtc->ops->atomic_disable(exynos_crtc); + ++ spin_lock_irq(&crtc->dev->event_lock); + if (crtc->state->event && !crtc->state->active) { +- spin_lock_irq(&crtc->dev->event_lock); + drm_crtc_send_vblank_event(crtc, crtc->state->event); +- spin_unlock_irq(&crtc->dev->event_lock); +- + crtc->state->event = NULL; + } ++ spin_unlock_irq(&crtc->dev->event_lock); + } + + static int exynos_crtc_atomic_check(struct drm_crtc *crtc, +-- +2.43.0 + diff --git a/patches.suse/drm-i915-Add-missing-CCS-documentation.patch b/patches.suse/drm-i915-Add-missing-CCS-documentation.patch new file mode 100644 index 0000000..38d6434 --- /dev/null +++ b/patches.suse/drm-i915-Add-missing-CCS-documentation.patch @@ -0,0 +1,74 @@ +From d38d753da7f7c9c4739e3e9ca3c986fa2c1b8c98 Mon Sep 17 00:00:00 2001 +From: Rodrigo Vivi +Date: Tue, 26 Sep 2023 12:51:06 -0400 +Subject: [PATCH] drm/i915: Add missing CCS documentation +Git-commit: d38d753da7f7c9c4739e3e9ca3c986fa2c1b8c98 +Patch-mainline: v6.7-rc1 +References: git-fixes + +Let's introduce the basic documentation about CCS. +While doing that, also removed the legacy execution flag name. That flag +simply doesn't exist for CCS and it is not needed on current context +submission. Those flag names are only needed on legacy context, +while on new ones we only need to pass the engine ID. + +It is worth mention that this documentation should probably live with +the engine definitions rather than in the i915.rst file directly and +that more updates are likely need in this section. But this should +come later. + +V2: Overall improvements from Matt and Tvrtko. + +Fixes: 944823c94639 ("drm/i915/xehp: Define compute class and engine") +Cc: Matt Roper +Cc: Sushma Venkatesh Reddy +Cc: Joonas Lahtinen +Cc: Tvrtko Ursulin +Signed-off-by: Rodrigo Vivi +Acked-by: Tvrtko Ursulin +Reviewed-by: Matt Roper +Link: https://patchwork.freedesktop.org/patch/msgid/20230926165107.23440-1-rodrigo.vivi@intel.com +Acked-by: Takashi Iwai + +--- + Documentation/gpu/i915.rst | 23 +++++++++++------------ + 1 file changed, 11 insertions(+), 12 deletions(-) + +diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst +index 378e825754d5..13de8bcaaa29 100644 +--- a/Documentation/gpu/i915.rst ++++ b/Documentation/gpu/i915.rst +@@ -267,19 +267,18 @@ i915 driver. + Intel GPU Basics + ---------------- + +-An Intel GPU has multiple engines. There are several engine types. ++An Intel GPU has multiple engines. There are several engine types: + +-- RCS engine is for rendering 3D and performing compute, this is named +- `I915_EXEC_RENDER` in user space. +-- BCS is a blitting (copy) engine, this is named `I915_EXEC_BLT` in user +- space. +-- VCS is a video encode and decode engine, this is named `I915_EXEC_BSD` +- in user space +-- VECS is video enhancement engine, this is named `I915_EXEC_VEBOX` in user +- space. +-- The enumeration `I915_EXEC_DEFAULT` does not refer to specific engine; +- instead it is to be used by user space to specify a default rendering +- engine (for 3D) that may or may not be the same as RCS. ++- Render Command Streamer (RCS). An engine for rendering 3D and ++ performing compute. ++- Blitting Command Streamer (BCS). An engine for performing blitting and/or ++ copying operations. ++- Video Command Streamer. An engine used for video encoding and decoding. Also ++ sometimes called 'BSD' in hardware documentation. ++- Video Enhancement Command Streamer (VECS). An engine for video enhancement. ++ Also sometimes called 'VEBOX' in hardware documentation. ++- Compute Command Streamer (CCS). An engine that has access to the media and ++ GPGPU pipelines, but not the 3D pipeline. + + The Intel GPU family is a family of integrated GPU's using Unified + Memory Access. For having the GPU "do work", user space will feed the +-- +2.43.0 + diff --git a/patches.suse/drm-i915-Call-intel_pre_plane_updates-also-for-pipes.patch b/patches.suse/drm-i915-Call-intel_pre_plane_updates-also-for-pipes.patch new file mode 100644 index 0000000..367c86b --- /dev/null +++ b/patches.suse/drm-i915-Call-intel_pre_plane_updates-also-for-pipes.patch @@ -0,0 +1,50 @@ +From d21a3962d3042e6f56ad324cf18bdd64a1e6ecfa Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Tue, 21 Nov 2023 07:43:15 +0200 +Subject: [PATCH] drm/i915: Call intel_pre_plane_updates() also for pipes getting enabled +Mime-version: 1.0 +Content-type: text/plain; charset=UTF-8 +Content-transfer-encoding: 8bit +Git-commit: d21a3962d3042e6f56ad324cf18bdd64a1e6ecfa +Patch-mainline: v6.7-rc4 +Alt-commit: e0d5ce11ed0a21bb2bf328ad82fd261783c7ad88 +References: git-fixes + +We used to call intel_pre_plane_updates() for any pipe going through +a modeset whether the pipe was previously enabled or not. This in +fact needed to apply all the necessary clock gating workarounds/etc. +Restore the correct behaviour. + +Fixes: 39919997322f ("drm/i915: Disable all planes before modesetting any pipes") +Reviewed-by: Jani Nikula +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20231121054324.9988-3-ville.syrjala@linux.intel.com +(cherry picked from commit e0d5ce11ed0a21bb2bf328ad82fd261783c7ad88) + +Signed-off-by: Jani Nikula +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/i915/display/intel_display.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c +index 28d85e1e858e..a2a806262c9e 100644 +--- a/drivers/gpu/drm/i915/display/intel_display.c ++++ b/drivers/gpu/drm/i915/display/intel_display.c +@@ -6853,10 +6853,11 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state) + if (!intel_crtc_needs_modeset(new_crtc_state)) + continue; + ++ intel_pre_plane_update(state, crtc); ++ + if (!old_crtc_state->hw.active) + continue; + +- intel_pre_plane_update(state, crtc); + intel_crtc_disable_planes(state, crtc); + } + +-- +2.43.0 + diff --git a/patches.suse/drm-i915-gt-Use-i915_vm_put-on-ppgtt_create-error-pa.patch b/patches.suse/drm-i915-gt-Use-i915_vm_put-on-ppgtt_create-error-pa.patch new file mode 100644 index 0000000..ee65202 --- /dev/null +++ b/patches.suse/drm-i915-gt-Use-i915_vm_put-on-ppgtt_create-error-pa.patch @@ -0,0 +1,218 @@ +From 20e377e7b2e7c327039f10db80ba5bcc1f6c882d Mon Sep 17 00:00:00 2001 +From: Chris Wilson +Date: Mon, 26 Sep 2022 16:33:33 +0100 +Subject: [PATCH] drm/i915/gt: Use i915_vm_put on ppgtt_create error paths +Mime-version: 1.0 +Content-type: text/plain; charset=UTF-8 +Content-transfer-encoding: 8bit +Git-commit: 20e377e7b2e7c327039f10db80ba5bcc1f6c882d +Patch-mainline: v6.1-rc1 +Alt-commit: c286558f58535cf97b717b946d6c96d774a09d17 +References: git-fixes + +Now that the scratch page and page directories have a reference back to +the i915_address_space, we cannot do an immediate free of the ppgtt upon +error as those buffer objects will perform a later i915_vm_put in their +deferred frees. + +The downside is that by replacing the onion unwind along the error +paths, the ppgtt cleanup must handle a partially constructed vm. This +includes ensuring that the vm->cleanup is set prior to the error path. + +Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6900 +Signed-off-by: Chris Wilson +Fixes: 4d8151ae5329 ("drm/i915: Don't free shared locks while shared") +Cc: Thomas Hellström +Cc: Matthew Auld +Cc: # v5.14+ +Reviewed-by: Matthew Auld +Signed-off-by: Matthew Auld +Link: https://patchwork.freedesktop.org/patch/msgid/20220926153333.102195-1-matthew.auld@intel.com +(cherry picked from commit c286558f58535cf97b717b946d6c96d774a09d17) + +Signed-off-by: Tvrtko Ursulin +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 16 ++++---- + drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 58 ++++++++++++++-------------- + drivers/gpu/drm/i915/gt/intel_gtt.c | 3 ++ + 3 files changed, 41 insertions(+), 36 deletions(-) + +diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c +index 1bb766c79dcb..5aaacc53fa4c 100644 +--- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c ++++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c +@@ -247,6 +247,7 @@ static int gen6_ppgtt_init_scratch(struct gen6_ppgtt *ppgtt) + i915_gem_object_put(vm->scratch[1]); + err_scratch0: + i915_gem_object_put(vm->scratch[0]); ++ vm->scratch[0] = NULL; + return ret; + } + +@@ -268,9 +269,10 @@ static void gen6_ppgtt_cleanup(struct i915_address_space *vm) + gen6_ppgtt_free_pd(ppgtt); + free_scratch(vm); + +- mutex_destroy(&ppgtt->flush); ++ if (ppgtt->base.pd) ++ free_pd(&ppgtt->base.vm, ppgtt->base.pd); + +- free_pd(&ppgtt->base.vm, ppgtt->base.pd); ++ mutex_destroy(&ppgtt->flush); + } + + static void pd_vma_bind(struct i915_address_space *vm, +@@ -449,19 +451,17 @@ struct i915_ppgtt *gen6_ppgtt_create(struct intel_gt *gt) + + err = gen6_ppgtt_init_scratch(ppgtt); + if (err) +- goto err_free; ++ goto err_put; + + ppgtt->base.pd = gen6_alloc_top_pd(ppgtt); + if (IS_ERR(ppgtt->base.pd)) { + err = PTR_ERR(ppgtt->base.pd); +- goto err_scratch; ++ goto err_put; + } + + return &ppgtt->base; + +-err_scratch: +- free_scratch(&ppgtt->base.vm); +-err_free: +- kfree(ppgtt); ++err_put: ++ i915_vm_put(&ppgtt->base.vm); + return ERR_PTR(err); + } +diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c +index c7bd5d71b03e..2128b7a72a25 100644 +--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c ++++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c +@@ -196,7 +196,10 @@ static void gen8_ppgtt_cleanup(struct i915_address_space *vm) + if (intel_vgpu_active(vm->i915)) + gen8_ppgtt_notify_vgt(ppgtt, false); + +- __gen8_ppgtt_cleanup(vm, ppgtt->pd, gen8_pd_top_count(vm), vm->top); ++ if (ppgtt->pd) ++ __gen8_ppgtt_cleanup(vm, ppgtt->pd, ++ gen8_pd_top_count(vm), vm->top); ++ + free_scratch(vm); + } + +@@ -803,8 +806,10 @@ static int gen8_init_scratch(struct i915_address_space *vm) + struct drm_i915_gem_object *obj; + + obj = vm->alloc_pt_dma(vm, I915_GTT_PAGE_SIZE_4K); +- if (IS_ERR(obj)) ++ if (IS_ERR(obj)) { ++ ret = PTR_ERR(obj); + goto free_scratch; ++ } + + ret = map_pt_dma(vm, obj); + if (ret) { +@@ -823,7 +828,8 @@ static int gen8_init_scratch(struct i915_address_space *vm) + free_scratch: + while (i--) + i915_gem_object_put(vm->scratch[i]); +- return -ENOMEM; ++ vm->scratch[0] = NULL; ++ return ret; + } + + static int gen8_preallocate_top_level_pdp(struct i915_ppgtt *ppgtt) +@@ -901,6 +907,7 @@ gen8_alloc_top_pd(struct i915_address_space *vm) + struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt, + unsigned long lmem_pt_obj_flags) + { ++ struct i915_page_directory *pd; + struct i915_ppgtt *ppgtt; + int err; + +@@ -946,21 +953,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt, + ppgtt->vm.alloc_scratch_dma = alloc_pt_dma; + } + +- err = gen8_init_scratch(&ppgtt->vm); +- if (err) +- goto err_free; +- +- ppgtt->pd = gen8_alloc_top_pd(&ppgtt->vm); +- if (IS_ERR(ppgtt->pd)) { +- err = PTR_ERR(ppgtt->pd); +- goto err_free_scratch; +- } +- +- if (!i915_vm_is_4lvl(&ppgtt->vm)) { +- err = gen8_preallocate_top_level_pdp(ppgtt); +- if (err) +- goto err_free_pd; +- } ++ ppgtt->vm.pte_encode = gen8_pte_encode; + + ppgtt->vm.bind_async_flags = I915_VMA_LOCAL_BIND; + ppgtt->vm.insert_entries = gen8_ppgtt_insert; +@@ -971,22 +964,31 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt, + ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc; + ppgtt->vm.clear_range = gen8_ppgtt_clear; + ppgtt->vm.foreach = gen8_ppgtt_foreach; ++ ppgtt->vm.cleanup = gen8_ppgtt_cleanup; + +- ppgtt->vm.pte_encode = gen8_pte_encode; ++ err = gen8_init_scratch(&ppgtt->vm); ++ if (err) ++ goto err_put; ++ ++ pd = gen8_alloc_top_pd(&ppgtt->vm); ++ if (IS_ERR(pd)) { ++ err = PTR_ERR(pd); ++ goto err_put; ++ } ++ ppgtt->pd = pd; ++ ++ if (!i915_vm_is_4lvl(&ppgtt->vm)) { ++ err = gen8_preallocate_top_level_pdp(ppgtt); ++ if (err) ++ goto err_put; ++ } + + if (intel_vgpu_active(gt->i915)) + gen8_ppgtt_notify_vgt(ppgtt, true); + +- ppgtt->vm.cleanup = gen8_ppgtt_cleanup; +- + return ppgtt; + +-err_free_pd: +- __gen8_ppgtt_cleanup(&ppgtt->vm, ppgtt->pd, +- gen8_pd_top_count(&ppgtt->vm), ppgtt->vm.top); +-err_free_scratch: +- free_scratch(&ppgtt->vm); +-err_free: +- kfree(ppgtt); ++err_put: ++ i915_vm_put(&ppgtt->vm); + return ERR_PTR(err); + } +diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c +index b67831833c9a..2eaeba14319e 100644 +--- a/drivers/gpu/drm/i915/gt/intel_gtt.c ++++ b/drivers/gpu/drm/i915/gt/intel_gtt.c +@@ -405,6 +405,9 @@ void free_scratch(struct i915_address_space *vm) + { + int i; + ++ if (!vm->scratch[0]) ++ return; ++ + for (i = 0; i <= vm->top; i++) + i915_gem_object_put(vm->scratch[i]); + } +-- +2.43.0 + diff --git a/patches.suse/drm-panel-Move-AUX-B116XW03-out-of-panel-edp-back-to.patch b/patches.suse/drm-panel-Move-AUX-B116XW03-out-of-panel-edp-back-to.patch new file mode 100644 index 0000000..c70c164 --- /dev/null +++ b/patches.suse/drm-panel-Move-AUX-B116XW03-out-of-panel-edp-back-to.patch @@ -0,0 +1,157 @@ +From ad3e33fe071dffea07279f96dab4f3773c430fe2 Mon Sep 17 00:00:00 2001 +From: Douglas Anderson +Date: Mon, 25 Sep 2023 15:00:11 -0700 +Subject: [PATCH] drm/panel: Move AUX B116XW03 out of panel-edp back to panel-simple +Git-commit: ad3e33fe071dffea07279f96dab4f3773c430fe2 +Patch-mainline: v6.6-rc7 +References: git-fixes + +In commit 5f04e7ce392d ("drm/panel-edp: Split eDP panels out of +panel-simple") I moved a pile of panels out of panel-simple driver +into the newly created panel-edp driver. One of those panels, however, +shouldn't have been moved. + +As is clear from commit e35e305eff0f ("drm/panel: simple: Add AUO +B116XW03 panel support"), AUX B116XW03 is an LVDS panel. It's used in +exynos5250-snow and exynos5420-peach-pit where it's clear that the +panel is hooked up with LVDS. Furthermore, searching for datasheets I +found one that makes it clear that this panel is LVDS. + +As far as I can tell, I got confused because in commit 88d3457ceb82 +("drm/panel: auo,b116xw03: fix flash backlight when power on") Jitao +Shi added "DRM_MODE_CONNECTOR_eDP". That seems wrong. Looking at the +downstream ChromeOS trees, it seems like some Mediatek boards are +using a panel that they call "auo,b116xw03" that's an eDP panel. The +best I can guess is that they actually have a different panel that has +similar timing. If so then the proper panel should be used or they +should switch to the generic "edp-panel" compatible. + +When moving this back to panel-edp, I wasn't sure what to use for +.bus_flags and .bus_format and whether to add the extra "enable" delay +from commit 88d3457ceb82 ("drm/panel: auo,b116xw03: fix flash +backlight when power on"). I've added formats/flags/delays based on my +(inexpert) analysis of the datasheet. These are untested. + +Note: if/when this is backported to stable, we might run into some +trouble. Specifically, before 474c162878ba ("arm64: dts: mt8183: +Jacuzzi: Move panel under aux-bus") this panel was used by +"mt8183-kukui-jacuzzi", which assumed it was an eDP panel. I don't +know what to suggest for that other than someone making up a bogus +panel for jacuzzi that's just for the stable channel. + +Fixes: 88d3457ceb82 ("drm/panel: auo,b116xw03: fix flash backlight when power on") +Fixes: 5f04e7ce392d ("drm/panel-edp: Split eDP panels out of panel-simple") +Tested-by: Anton Bambura +Acked-by: Hsin-Yi Wang +Signed-off-by: Douglas Anderson +Link: https://patchwork.freedesktop.org/patch/msgid/20230925150010.1.Iff672233861bcc4cf25a7ad0a81308adc3bda8a4@changeid +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/panel/panel-edp.c | 29 ----------------------- + drivers/gpu/drm/panel/panel-simple.c | 35 ++++++++++++++++++++++++++++ + 2 files changed, 35 insertions(+), 29 deletions(-) + +diff --git a/drivers/gpu/drm/panel/panel-edp.c b/drivers/gpu/drm/panel/panel-edp.c +index feb665df35a1..95c8472d878a 100644 +--- a/drivers/gpu/drm/panel/panel-edp.c ++++ b/drivers/gpu/drm/panel/panel-edp.c +@@ -976,32 +976,6 @@ static const struct panel_desc auo_b116xak01 = { + }, + }; + +-static const struct drm_display_mode auo_b116xw03_mode = { +- .clock = 70589, +- .hdisplay = 1366, +- .hsync_start = 1366 + 40, +- .hsync_end = 1366 + 40 + 40, +- .htotal = 1366 + 40 + 40 + 32, +- .vdisplay = 768, +- .vsync_start = 768 + 10, +- .vsync_end = 768 + 10 + 12, +- .vtotal = 768 + 10 + 12 + 6, +- .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, +-}; +- +-static const struct panel_desc auo_b116xw03 = { +- .modes = &auo_b116xw03_mode, +- .num_modes = 1, +- .bpc = 6, +- .size = { +- .width = 256, +- .height = 144, +- }, +- .delay = { +- .enable = 400, +- }, +-}; +- + static const struct drm_display_mode auo_b133han05_mode = { + .clock = 142600, + .hdisplay = 1920, +@@ -1725,9 +1699,6 @@ static const struct of_device_id platform_of_match[] = { + }, { + .compatible = "auo,b116xa01", + .data = &auo_b116xak01, +- }, { +- .compatible = "auo,b116xw03", +- .data = &auo_b116xw03, + }, { + .compatible = "auo,b133han05", + .data = &auo_b133han05, +diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c +index 95959dcc6e0e..dd7928d9570f 100644 +--- a/drivers/gpu/drm/panel/panel-simple.c ++++ b/drivers/gpu/drm/panel/panel-simple.c +@@ -919,6 +919,38 @@ static const struct panel_desc auo_b101xtn01 = { + }, + }; + ++static const struct drm_display_mode auo_b116xw03_mode = { ++ .clock = 70589, ++ .hdisplay = 1366, ++ .hsync_start = 1366 + 40, ++ .hsync_end = 1366 + 40 + 40, ++ .htotal = 1366 + 40 + 40 + 32, ++ .vdisplay = 768, ++ .vsync_start = 768 + 10, ++ .vsync_end = 768 + 10 + 12, ++ .vtotal = 768 + 10 + 12 + 6, ++ .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, ++}; ++ ++static const struct panel_desc auo_b116xw03 = { ++ .modes = &auo_b116xw03_mode, ++ .num_modes = 1, ++ .bpc = 6, ++ .size = { ++ .width = 256, ++ .height = 144, ++ }, ++ .delay = { ++ .prepare = 1, ++ .enable = 200, ++ .disable = 200, ++ .unprepare = 500, ++ }, ++ .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, ++ .bus_flags = DRM_BUS_FLAG_DE_HIGH, ++ .connector_type = DRM_MODE_CONNECTOR_LVDS, ++}; ++ + static const struct display_timing auo_g070vvn01_timings = { + .pixelclock = { 33300000, 34209000, 45000000 }, + .hactive = { 800, 800, 800 }, +@@ -4102,6 +4134,9 @@ static const struct of_device_id platform_of_match[] = { + }, { + .compatible = "auo,b101xtn01", + .data = &auo_b101xtn01, ++ }, { ++ .compatible = "auo,b116xw03", ++ .data = &auo_b116xw03, + }, { + .compatible = "auo,g070vvn01", + .data = &auo_g070vvn01, +-- +2.43.0 + diff --git a/patches.suse/drm-panel-auo-b101uan08.3-Fine-tune-the-panel-power-.patch b/patches.suse/drm-panel-auo-b101uan08.3-Fine-tune-the-panel-power-.patch new file mode 100644 index 0000000..53368ec --- /dev/null +++ b/patches.suse/drm-panel-auo-b101uan08.3-Fine-tune-the-panel-power-.patch @@ -0,0 +1,37 @@ +From 6965809e526917b73c8f9178173184dcf13cec4b Mon Sep 17 00:00:00 2001 +From: Xuxin Xiong +Date: Tue, 14 Nov 2023 12:42:05 +0800 +Subject: [PATCH] drm/panel: auo,b101uan08.3: Fine tune the panel power sequence +Git-commit: 6965809e526917b73c8f9178173184dcf13cec4b +Patch-mainline: v6.7-rc3 +References: git-fixes + +For "auo,b101uan08.3" this panel, it is stipulated in the panel spec that +MIPI needs to keep the LP11 state before the lcm_reset pin is pulled high. + +Fixes: 56ad624b4cb5 ("drm/panel: support for auo, b101uan08.3 wuxga dsi video mode panel") +Signed-off-by: Xuxin Xiong +Reviewed-by: Douglas Anderson +Signed-off-by: Douglas Anderson +Link: https://patchwork.freedesktop.org/patch/msgid/20231114044205.613421-1-xuxinxiong@huaqin.corp-partner.google.com +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c +index 9323e7b9e384..a287be1aaf70 100644 +--- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c ++++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c +@@ -1709,6 +1709,7 @@ static const struct panel_desc auo_b101uan08_3_desc = { + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM, + .init_cmds = auo_b101uan08_3_init_cmd, ++ .lp11_before_reset = true, + }; + + static const struct drm_display_mode boe_tv105wum_nw0_default_mode = { +-- +2.43.0 + diff --git a/patches.suse/drm-panel-boe-tv101wum-nl6-Fine-tune-the-panel-power.patch b/patches.suse/drm-panel-boe-tv101wum-nl6-Fine-tune-the-panel-power.patch new file mode 100644 index 0000000..a851f33 --- /dev/null +++ b/patches.suse/drm-panel-boe-tv101wum-nl6-Fine-tune-the-panel-power.patch @@ -0,0 +1,52 @@ +From 812562b8d881ce6d33fed8052b3a10b718430fb5 Mon Sep 17 00:00:00 2001 +From: Shuijing Li +Date: Mon, 15 May 2023 17:49:55 +0800 +Subject: [PATCH] drm/panel: boe-tv101wum-nl6: Fine tune the panel power sequence +Git-commit: 812562b8d881ce6d33fed8052b3a10b718430fb5 +Patch-mainline: v6.5-rc1 +References: git-fixes + +For "boe,tv105wum-nw0" this special panel, it is stipulated in +the panel spec that MIPI needs to keep the LP11 state before +the lcm_reset pin is pulled high. + +Signed-off-by: Shuijing Li +Signed-off-by: Xinlei Lee +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Neil Armstrong +Link: https://patchwork.freedesktop.org/patch/msgid/20230515094955.15982-3-shuijing.li@mediatek.com +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c ++++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c +@@ -36,6 +36,7 @@ struct panel_desc { + const struct panel_init_cmd *init_cmds; + unsigned int lanes; + bool discharge_on_disable; ++ bool lp11_before_reset; + }; + + struct boe_panel { +@@ -1269,6 +1270,10 @@ static int boe_panel_prepare(struct drm_ + + usleep_range(10000, 11000); + ++ if (boe->desc->lp11_before_reset) { ++ mipi_dsi_dcs_nop(boe->dsi); ++ usleep_range(1000, 2000); ++ } + gpiod_set_value(boe->enable_gpio, 1); + usleep_range(1000, 2000); + gpiod_set_value(boe->enable_gpio, 0); +@@ -1495,6 +1500,7 @@ static const struct panel_desc boe_tv105 + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM, + .init_cmds = boe_init_cmd, ++ .lp11_before_reset = true, + }; + + static int boe_panel_get_modes(struct drm_panel *panel, diff --git a/patches.suse/drm-panel-orientation-quirks-Add-quirk-for-Acer-Swit.patch b/patches.suse/drm-panel-orientation-quirks-Add-quirk-for-Acer-Swit.patch new file mode 100644 index 0000000..519960d --- /dev/null +++ b/patches.suse/drm-panel-orientation-quirks-Add-quirk-for-Acer-Swit.patch @@ -0,0 +1,42 @@ +From 653f2d94fcda200b02bd79cea2e0307b26c1b747 Mon Sep 17 00:00:00 2001 +From: Hans de Goede +Date: Sun, 6 Nov 2022 22:50:52 +0100 +Subject: [PATCH] drm: panel-orientation-quirks: Add quirk for Acer Switch V 10 (SW5-017) +Git-commit: 653f2d94fcda200b02bd79cea2e0307b26c1b747 +Patch-mainline: v6.1-rc5 +References: git-fixes + +Like the Acer Switch One 10 S1003, for which there already is a quirk, +the Acer Switch V 10 (SW5-017) has a 800x1280 portrait screen mounted +in the tablet part of a landscape oriented 2-in-1. Add a quirk for this. + +Cc: Rudolf Polzer +Signed-off-by: Hans de Goede +Acked-by: Simon Ser +Link: https://patchwork.freedesktop.org/patch/msgid/20221106215052.66995-1-hdegoede@redhat.com +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/drm_panel_orientation_quirks.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/drivers/gpu/drm/drm_panel_orientation_quirks.c b/drivers/gpu/drm/drm_panel_orientation_quirks.c +index f0f6fa306521..52d8800a8ab8 100644 +--- a/drivers/gpu/drm/drm_panel_orientation_quirks.c ++++ b/drivers/gpu/drm/drm_panel_orientation_quirks.c +@@ -134,6 +134,12 @@ static const struct dmi_system_id orientation_data[] = { + DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "One S1003"), + }, + .driver_data = (void *)&lcd800x1280_rightside_up, ++ }, { /* Acer Switch V 10 (SW5-017) */ ++ .matches = { ++ DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Acer"), ++ DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "SW5-017"), ++ }, ++ .driver_data = (void *)&lcd800x1280_rightside_up, + }, { /* Anbernic Win600 */ + .matches = { + DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "Anbernic"), +-- +2.43.0 + diff --git a/patches.suse/drm-rockchip-dsi-Clean-up-usage_mode-when-failing-to.patch b/patches.suse/drm-rockchip-dsi-Clean-up-usage_mode-when-failing-to.patch new file mode 100644 index 0000000..6abca3c --- /dev/null +++ b/patches.suse/drm-rockchip-dsi-Clean-up-usage_mode-when-failing-to.patch @@ -0,0 +1,72 @@ +From 0be67e0556e469c57100ffe3c90df90abc796f3b Mon Sep 17 00:00:00 2001 +From: Brian Norris +Date: Wed, 19 Oct 2022 17:03:48 -0700 +Subject: [PATCH] drm/rockchip: dsi: Clean up 'usage_mode' when failing to attach +Git-commit: 0be67e0556e469c57100ffe3c90df90abc796f3b +Patch-mainline: v6.1-rc4 +References: git-fixes + +If we fail to attach the first time (especially: EPROBE_DEFER), we fail +to clean up 'usage_mode', and thus will fail to attach on any subsequent +attempts, with "dsi controller already in use". + +Re-set to DW_DSI_USAGE_IDLE on attach failure. + +This is especially common to hit when enabling asynchronous probe on a +duel-DSI system (such as RK3399 Gru/Scarlet), such that we're more +likely to fail dw_mipi_dsi_rockchip_find_second() the first time. + +Fixes: 71f68fe7f121 ("drm/rockchip: dsi: add ability to work as a phy instead of full dsi") +Cc: +Signed-off-by: Brian Norris +Signed-off-by: Heiko Stuebner +Link: https://patchwork.freedesktop.org/patch/msgid/20221019170255.1.Ia68dfb27b835d31d22bfe23812baf366ee1c6eac@changeid +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 16 ++++++++++++---- + 1 file changed, 12 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +index bf6948125b84..d222c6811207 100644 +--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c ++++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +@@ -1051,23 +1051,31 @@ static int dw_mipi_dsi_rockchip_host_attach(void *priv_data, + if (ret) { + DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n", + ret); +- return ret; ++ goto out; + } + + second = dw_mipi_dsi_rockchip_find_second(dsi); +- if (IS_ERR(second)) +- return PTR_ERR(second); ++ if (IS_ERR(second)) { ++ ret = PTR_ERR(second); ++ goto out; ++ } + if (second) { + ret = component_add(second, &dw_mipi_dsi_rockchip_ops); + if (ret) { + DRM_DEV_ERROR(second, + "Failed to register component: %d\n", + ret); +- return ret; ++ goto out; + } + } + + return 0; ++ ++out: ++ mutex_lock(&dsi->usage_mutex); ++ dsi->usage_mode = DW_DSI_USAGE_IDLE; ++ mutex_unlock(&dsi->usage_mutex); ++ return ret; + } + + static int dw_mipi_dsi_rockchip_host_detach(void *priv_data, +-- +2.43.0 + diff --git a/patches.suse/drm-ttm-Don-t-leak-a-resource-on-eviction-error.patch b/patches.suse/drm-ttm-Don-t-leak-a-resource-on-eviction-error.patch new file mode 100644 index 0000000..27dffc6 --- /dev/null +++ b/patches.suse/drm-ttm-Don-t-leak-a-resource-on-eviction-error.patch @@ -0,0 +1,72 @@ +From e8188c461ee015ba0b9ab2fc82dbd5ebca5a5532 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= +Date: Mon, 26 Jun 2023 11:14:49 +0200 +Subject: [PATCH] drm/ttm: Don't leak a resource on eviction error +Mime-version: 1.0 +Content-type: text/plain; charset=UTF-8 +Content-transfer-encoding: 8bit +Git-commit: e8188c461ee015ba0b9ab2fc82dbd5ebca5a5532 +Patch-mainline: v6.5-rc2 +References: git-fixes + +On eviction errors other than -EMULTIHOP we were leaking a resource. +Fix. + +V2: +- Avoid yet another goto (Andi Shyti) + +Fixes: 403797925768 ("drm/ttm: Fix multihop assert on eviction.") +Cc: Andrey Grodzovsky +Cc: Christian König +Cc: Christian Koenig +Cc: Huang Rui +Cc: dri-devel@lists.freedesktop.org +Cc: # v5.15+ +Signed-off-by: Thomas Hellström +Reviewed-by: Nirmoy Das #v1 +Reviewed-by: Andi Shyti +Reviewed-by: Christian König +Link: https://patchwork.freedesktop.org/patch/msgid/20230626091450.14757-4-thomas.hellstrom@linux.intel.com +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/ttm/ttm_bo.c | 22 +++++++++++----------- + 1 file changed, 11 insertions(+), 11 deletions(-) + +diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c +index bd5dae4d1624..d364639a2752 100644 +--- a/drivers/gpu/drm/ttm/ttm_bo.c ++++ b/drivers/gpu/drm/ttm/ttm_bo.c +@@ -458,18 +458,18 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo, + goto out; + } + +-bounce: +- ret = ttm_bo_handle_move_mem(bo, evict_mem, true, ctx, &hop); +- if (ret == -EMULTIHOP) { ++ do { ++ ret = ttm_bo_handle_move_mem(bo, evict_mem, true, ctx, &hop); ++ if (ret != -EMULTIHOP) ++ break; ++ + ret = ttm_bo_bounce_temp_buffer(bo, &evict_mem, ctx, &hop); +- if (ret) { +- if (ret != -ERESTARTSYS && ret != -EINTR) +- pr_err("Buffer eviction failed\n"); +- ttm_resource_free(bo, &evict_mem); +- goto out; +- } +- /* try and move to final place now. */ +- goto bounce; ++ } while (!ret); ++ ++ if (ret) { ++ ttm_resource_free(bo, &evict_mem); ++ if (ret != -ERESTARTSYS && ret != -EINTR) ++ pr_err("Buffer eviction failed\n"); + } + out: + return ret; +-- +2.43.0 + diff --git a/patches.suse/drm-ttm-Don-t-print-error-message-if-eviction-was-in.patch b/patches.suse/drm-ttm-Don-t-print-error-message-if-eviction-was-in.patch new file mode 100644 index 0000000..c8a047b --- /dev/null +++ b/patches.suse/drm-ttm-Don-t-print-error-message-if-eviction-was-in.patch @@ -0,0 +1,41 @@ +From 8ab3b0663e279ab550bc2c0b5d602960e8b94e02 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= +Date: Tue, 7 Mar 2023 15:46:19 +0100 +Subject: [PATCH] drm/ttm: Don't print error message if eviction was interrupted +Mime-version: 1.0 +Content-type: text/plain; charset=UTF-8 +Content-transfer-encoding: 8bit +Git-commit: 8ab3b0663e279ab550bc2c0b5d602960e8b94e02 +Patch-mainline: v6.4-rc1 +References: git-fixes + +Avoid printing an error message if eviction was interrupted by, +for example, the user pressing CTRL-C. That may happen if eviction +is waiting for something, like for example a free batch-buffer. + +Signed-off-by: Thomas Hellström +Reviewed-by: Christian König +Link: https://patchwork.freedesktop.org/patch/msgid/20230307144621.10748-6-thomas.hellstrom@linux.intel.com +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/ttm/ttm_bo.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c +index 882c2fa346f3..459f1b4440da 100644 +--- a/drivers/gpu/drm/ttm/ttm_bo.c ++++ b/drivers/gpu/drm/ttm/ttm_bo.c +@@ -464,7 +464,8 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo, + if (ret == -EMULTIHOP) { + ret = ttm_bo_bounce_temp_buffer(bo, &evict_mem, ctx, &hop); + if (ret) { +- pr_err("Buffer eviction failed\n"); ++ if (ret != -ERESTARTSYS && ret != -EINTR) ++ pr_err("Buffer eviction failed\n"); + ttm_resource_free(bo, &evict_mem); + goto out; + } +-- +2.43.0 + diff --git a/patches.suse/drm-vc4-Add-module-dependency-on-hdmi-codec.patch b/patches.suse/drm-vc4-Add-module-dependency-on-hdmi-codec.patch new file mode 100644 index 0000000..6a1f44f --- /dev/null +++ b/patches.suse/drm-vc4-Add-module-dependency-on-hdmi-codec.patch @@ -0,0 +1,55 @@ +From d1c0b7de4dfa5505cf7a1d6220aa72aace4435d0 Mon Sep 17 00:00:00 2001 +From: Maxime Ripard +Date: Fri, 2 Sep 2022 16:41:11 +0200 +Subject: [PATCH] drm/vc4: Add module dependency on hdmi-codec +Git-commit: d1c0b7de4dfa5505cf7a1d6220aa72aace4435d0 +Patch-mainline: v6.1-rc2 +References: git-fixes + +The VC4 HDMI controller driver relies on the HDMI codec ASoC driver. In +order to set it up properly, in vc4_hdmi_audio_init(), our HDMI driver +will register a device matching the HDMI codec driver, and then register +an ASoC card using that codec. + +However, if vc4 is compiled as a module, chances are that the hdmi-codec +driver will be too. In such a case, the module loader will have a very +narrow window to load the module between the device registration and the +card registration. + +If it fails to load the module in time, the card registration will fail +with EPROBE_DEFER, and we'll abort the audio initialisation, +unregistering the HDMI codec device in the process. + +The next time the bind callback will be run, it's likely that we end up +missing that window again, effectively preventing vc4 to probe entirely. + +In order to prevent this, we can create a soft dependency of the vc4 +driver on the HDMI codec one so that we're sure the HDMI codec will be +loaded before the VC4 module is, and thus we'll never end up in the +previous situation. + +Fixes: 91e99e113929 ("drm/vc4: hdmi: Register HDMI codec") +Reviewed-by: Javier Martinez Canillas +Signed-off-by: Maxime Ripard +Link: https://patchwork.freedesktop.org/patch/msgid/20220902144111.3424560-1-maxime@cerno.tech +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/vc4/vc4_drv.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/gpu/drm/vc4/vc4_drv.c b/drivers/gpu/drm/vc4/vc4_drv.c +index 292d1b6a01b6..3dc01af0f90f 100644 +--- a/drivers/gpu/drm/vc4/vc4_drv.c ++++ b/drivers/gpu/drm/vc4/vc4_drv.c +@@ -480,6 +480,7 @@ module_init(vc4_drm_register); + module_exit(vc4_drm_unregister); + + MODULE_ALIAS("platform:vc4-drm"); ++MODULE_SOFTDEP("pre: snd-soc-hdmi-codec"); + MODULE_DESCRIPTION("Broadcom VC4 DRM Driver"); + MODULE_AUTHOR("Eric Anholt "); + MODULE_LICENSE("GPL v2"); +-- +2.43.0 + diff --git a/patches.suse/media-dvb-frontends-avoid-stack-overflow-warnings-wi.patch b/patches.suse/media-dvb-frontends-avoid-stack-overflow-warnings-wi.patch new file mode 100644 index 0000000..334e82f --- /dev/null +++ b/patches.suse/media-dvb-frontends-avoid-stack-overflow-warnings-wi.patch @@ -0,0 +1,95 @@ +From 7a4cf27d1f0538f779bf31b8c99eda394e277119 Mon Sep 17 00:00:00 2001 +From: Arnd Bergmann +Date: Fri, 16 Feb 2024 17:31:44 +0100 +Subject: [PATCH] media: dvb-frontends: avoid stack overflow warnings with clang +Git-commit: 7a4cf27d1f0538f779bf31b8c99eda394e277119 +Patch-mainline: v6.9-rc1 +References: git-fixes + +A previous patch worked around a KASAN issue in stv0367, now a similar +problem showed up with clang: + +drivers/media/dvb-frontends/stv0367.c:1222:12: error: stack frame size (3624) exceeds limit (2048) in 'stv0367ter_set_frontend' [-Werror,-Wframe-larger-than] + 1214 | static int stv0367ter_set_frontend(struct dvb_frontend *fe) + +Rework the stv0367_writereg() function to be simpler and mark both +register access functions as noinline_for_stack so the temporary +i2c_msg structures do not get duplicated on the stack when KASAN_STACK +is enabled. + +Fixes: 3cd890dbe2a4 ("media: dvb-frontends: fix i2c access helpers for KASAN") +Signed-off-by: Arnd Bergmann +Reviewed-by: Justin Stitt +Signed-off-by: Hans Verkuil +Acked-by: Takashi Iwai + +--- + drivers/media/dvb-frontends/stv0367.c | 34 +++++++-------------------- + 1 file changed, 8 insertions(+), 26 deletions(-) + +diff --git a/drivers/media/dvb-frontends/stv0367.c b/drivers/media/dvb-frontends/stv0367.c +index 48326434488c..72540ef4e5f8 100644 +--- a/drivers/media/dvb-frontends/stv0367.c ++++ b/drivers/media/dvb-frontends/stv0367.c +@@ -118,50 +118,32 @@ static const s32 stv0367cab_RF_LookUp2[RF_LOOKUP_TABLE2_SIZE][RF_LOOKUP_TABLE2_S + } + }; + +-static +-int stv0367_writeregs(struct stv0367_state *state, u16 reg, u8 *data, int len) ++static noinline_for_stack ++int stv0367_writereg(struct stv0367_state *state, u16 reg, u8 data) + { +- u8 buf[MAX_XFER_SIZE]; ++ u8 buf[3] = { MSB(reg), LSB(reg), data }; + struct i2c_msg msg = { + .addr = state->config->demod_address, + .flags = 0, + .buf = buf, +- .len = len + 2 ++ .len = 3, + }; + int ret; + +- if (2 + len > sizeof(buf)) { +- printk(KERN_WARNING +- "%s: i2c wr reg=%04x: len=%d is too big!\n", +- KBUILD_MODNAME, reg, len); +- return -EINVAL; +- } +- +- +- buf[0] = MSB(reg); +- buf[1] = LSB(reg); +- memcpy(buf + 2, data, len); +- + if (i2cdebug) + printk(KERN_DEBUG "%s: [%02x] %02x: %02x\n", __func__, +- state->config->demod_address, reg, buf[2]); ++ state->config->demod_address, reg, data); + + ret = i2c_transfer(state->i2c, &msg, 1); + if (ret != 1) + printk(KERN_ERR "%s: i2c write error! ([%02x] %02x: %02x)\n", +- __func__, state->config->demod_address, reg, buf[2]); ++ __func__, state->config->demod_address, reg, data); + + return (ret != 1) ? -EREMOTEIO : 0; + } + +-static int stv0367_writereg(struct stv0367_state *state, u16 reg, u8 data) +-{ +- u8 tmp = data; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */ +- +- return stv0367_writeregs(state, reg, &tmp, 1); +-} +- +-static u8 stv0367_readreg(struct stv0367_state *state, u16 reg) ++static noinline_for_stack ++u8 stv0367_readreg(struct stv0367_state *state, u16 reg) + { + u8 b0[] = { 0, 0 }; + u8 b1[] = { 0 }; +-- +2.43.0 + diff --git a/patches.suse/media-edia-dvbdev-fix-a-use-after-free.patch b/patches.suse/media-edia-dvbdev-fix-a-use-after-free.patch new file mode 100644 index 0000000..04654ef --- /dev/null +++ b/patches.suse/media-edia-dvbdev-fix-a-use-after-free.patch @@ -0,0 +1,79 @@ +From 8c64f4cdf4e6cc5682c52523713af8c39c94e6d5 Mon Sep 17 00:00:00 2001 +From: Zhipeng Lu +Date: Sat, 3 Feb 2024 14:40:43 +0100 +Subject: [PATCH] media: edia: dvbdev: fix a use-after-free +Git-commit: 8c64f4cdf4e6cc5682c52523713af8c39c94e6d5 +Patch-mainline: v6.9-rc1 +References: git-fixes + +In dvb_register_device, *pdvbdev is set equal to dvbdev, which is freed +in several error-handling paths. However, *pdvbdev is not set to NULL +after dvbdev's deallocation, causing use-after-frees in many places, +for example, in the following call chain: + +budget_register + |-> dvb_dmxdev_init + |-> dvb_register_device + |-> dvb_dmxdev_release + |-> dvb_unregister_device + |-> dvb_remove_device + |-> dvb_device_put + |-> kref_put + +When calling dvb_unregister_device, dmxdev->dvbdev (i.e. *pdvbdev in +dvb_register_device) could point to memory that had been freed in +dvb_register_device. Thereafter, this pointer is transferred to +kref_put and triggering a use-after-free. + +Link: https://lore.kernel.org/linux-media/20240203134046.3120099-1-alexious@zju.edu.cn +Fixes: b61901024776 ("V4L/DVB (5244): Dvbdev: fix illegal re-usage of fileoperations struct") +Signed-off-by: Zhipeng Lu +Signed-off-by: Mauro Carvalho Chehab +Acked-by: Takashi Iwai + +--- + drivers/media/dvb-core/dvbdev.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/drivers/media/dvb-core/dvbdev.c ++++ b/drivers/media/dvb-core/dvbdev.c +@@ -499,6 +499,7 @@ int dvb_register_device(struct dvb_adapt + dvbdevfops = kmemdup(template->fops, sizeof(*dvbdevfops), GFP_KERNEL); + if (!dvbdevfops) { + kfree(dvbdev); ++ *pdvbdev = NULL; + mutex_unlock(&dvbdev_register_lock); + return -ENOMEM; + } +@@ -507,6 +508,7 @@ int dvb_register_device(struct dvb_adapt + if (!new_node) { + kfree(dvbdevfops); + kfree(dvbdev); ++ *pdvbdev = NULL; + mutex_unlock(&dvbdev_register_lock); + return -ENOMEM; + } +@@ -539,6 +541,7 @@ int dvb_register_device(struct dvb_adapt + } + list_del (&dvbdev->list_head); + kfree(dvbdev); ++ *pdvbdev = NULL; + up_write(&minor_rwsem); + mutex_unlock(&dvbdev_register_lock); + return -EINVAL; +@@ -561,6 +564,7 @@ int dvb_register_device(struct dvb_adapt + dvb_media_device_free(dvbdev); + list_del (&dvbdev->list_head); + kfree(dvbdev); ++ *pdvbdev = NULL; + mutex_unlock(&dvbdev_register_lock); + return ret; + } +@@ -579,6 +583,7 @@ int dvb_register_device(struct dvb_adapt + dvb_media_device_free(dvbdev); + list_del (&dvbdev->list_head); + kfree(dvbdev); ++ *pdvbdev = NULL; + mutex_unlock(&dvbdev_register_lock); + return PTR_ERR(clsdev); + } diff --git a/patches.suse/media-em28xx-annotate-unchecked-call-to-media_device.patch b/patches.suse/media-em28xx-annotate-unchecked-call-to-media_device.patch new file mode 100644 index 0000000..e632bb0 --- /dev/null +++ b/patches.suse/media-em28xx-annotate-unchecked-call-to-media_device.patch @@ -0,0 +1,42 @@ +From fd61d77a3d28444b2635f0c8b5a2ecd6a4d94026 Mon Sep 17 00:00:00 2001 +From: Nikita Zhandarovich +Date: Fri, 12 Jan 2024 05:42:26 -0800 +Subject: [PATCH] media: em28xx: annotate unchecked call to media_device_register() +Git-commit: fd61d77a3d28444b2635f0c8b5a2ecd6a4d94026 +Patch-mainline: v6.9-rc1 +References: git-fixes + +Static analyzers generate alerts for an unchecked call to +`media_device_register()`. However, in this case, the device will work +reliably without the media controller API. + +Add a comment above the call to prevent future unnecessary changes. + +Suggested-by: Mauro Carvalho Chehab +Fixes: 37ecc7b1278f ("[media] em28xx: add media controller support") +Signed-off-by: Nikita Zhandarovich +Signed-off-by: Hans Verkuil +Acked-by: Takashi Iwai + +--- + drivers/media/usb/em28xx/em28xx-cards.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/media/usb/em28xx/em28xx-cards.c b/drivers/media/usb/em28xx/em28xx-cards.c +index 4d037c92af7c..bae76023cf71 100644 +--- a/drivers/media/usb/em28xx/em28xx-cards.c ++++ b/drivers/media/usb/em28xx/em28xx-cards.c +@@ -4094,6 +4094,10 @@ static int em28xx_usb_probe(struct usb_interface *intf, + * topology will likely change after the load of the em28xx subdrivers. + */ + #ifdef CONFIG_MEDIA_CONTROLLER ++ /* ++ * No need to check the return value, the device will still be ++ * usable without media controller API. ++ */ + retval = media_device_register(dev->media_dev); + #endif + +-- +2.43.0 + diff --git a/patches.suse/media-go7007-add-check-of-return-value-of-go7007_rea.patch b/patches.suse/media-go7007-add-check-of-return-value-of-go7007_rea.patch new file mode 100644 index 0000000..f7e2cb7 --- /dev/null +++ b/patches.suse/media-go7007-add-check-of-return-value-of-go7007_rea.patch @@ -0,0 +1,40 @@ +From 0b70530ee740861f4776ff724fcc25023df1799a Mon Sep 17 00:00:00 2001 +From: Daniil Dulov +Date: Sun, 11 Feb 2024 07:07:05 -0800 +Subject: [PATCH] media: go7007: add check of return value of go7007_read_addr() +Git-commit: 0b70530ee740861f4776ff724fcc25023df1799a +Patch-mainline: v6.9-rc1 +References: git-fixes + +If go7007_read_addr() returns error channel is not assigned a value. +In this case go to allocfail. + +Found by Linux Verification Center (linuxtesting.org) with SVACE. + +Fixes: 866b8695d67e ("Staging: add the go7007 video driver") +Signed-off-by: Daniil Dulov +Signed-off-by: Hans Verkuil +Acked-by: Takashi Iwai + +--- + drivers/media/usb/go7007/go7007-usb.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/media/usb/go7007/go7007-usb.c b/drivers/media/usb/go7007/go7007-usb.c +index eeb85981e02b..762c13e49bfa 100644 +--- a/drivers/media/usb/go7007/go7007-usb.c ++++ b/drivers/media/usb/go7007/go7007-usb.c +@@ -1201,7 +1201,9 @@ static int go7007_usb_probe(struct usb_interface *intf, + u16 channel; + + /* read channel number from GPIO[1:0] */ +- go7007_read_addr(go, 0x3c81, &channel); ++ if (go7007_read_addr(go, 0x3c81, &channel)) ++ goto allocfail; ++ + channel &= 0x3; + go->board_id = GO7007_BOARDID_ADLINK_MPG24; + usb->board = board = &board_adlink_mpg24; +-- +2.43.0 + diff --git a/patches.suse/media-go7007-fix-a-memleak-in-go7007_load_encoder.patch b/patches.suse/media-go7007-fix-a-memleak-in-go7007_load_encoder.patch new file mode 100644 index 0000000..db08c4b --- /dev/null +++ b/patches.suse/media-go7007-fix-a-memleak-in-go7007_load_encoder.patch @@ -0,0 +1,57 @@ +From b9b683844b01d171a72b9c0419a2d760d946ee12 Mon Sep 17 00:00:00 2001 +From: Zhipeng Lu +Date: Wed, 21 Feb 2024 12:37:13 +0800 +Subject: [PATCH] media: go7007: fix a memleak in go7007_load_encoder +Git-commit: b9b683844b01d171a72b9c0419a2d760d946ee12 +Patch-mainline: v6.9-rc1 +References: git-fixes + +In go7007_load_encoder, bounce(i.e. go->boot_fw), is allocated without +a deallocation thereafter. After the following call chain: + +saa7134_go7007_init + |-> go7007_boot_encoder + |-> go7007_load_encoder + |-> kfree(go) + +go is freed and thus bounce is leaked. + +Fixes: 95ef39403f89 ("[media] go7007: remember boot firmware") +Signed-off-by: Zhipeng Lu +Signed-off-by: Hans Verkuil +Acked-by: Takashi Iwai + +--- + drivers/media/usb/go7007/go7007-driver.c | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +diff --git a/drivers/media/usb/go7007/go7007-driver.c b/drivers/media/usb/go7007/go7007-driver.c +index 0c24e2984304..eb03f98b2ef1 100644 +--- a/drivers/media/usb/go7007/go7007-driver.c ++++ b/drivers/media/usb/go7007/go7007-driver.c +@@ -80,7 +80,7 @@ static int go7007_load_encoder(struct go7007 *go) + const struct firmware *fw_entry; + char fw_name[] = "go7007/go7007fw.bin"; + void *bounce; +- int fw_len, rv = 0; ++ int fw_len; + u16 intr_val, intr_data; + + if (go->boot_fw == NULL) { +@@ -109,9 +109,11 @@ static int go7007_load_encoder(struct go7007 *go) + go7007_read_interrupt(go, &intr_val, &intr_data) < 0 || + (intr_val & ~0x1) != 0x5a5a) { + v4l2_err(go, "error transferring firmware\n"); +- rv = -1; ++ kfree(go->boot_fw); ++ go->boot_fw = NULL; ++ return -1; + } +- return rv; ++ return 0; + } + + MODULE_FIRMWARE("go7007/go7007fw.bin"); +-- +2.43.0 + diff --git a/patches.suse/media-pvrusb2-fix-pvr2_stream_callback-casts.patch b/patches.suse/media-pvrusb2-fix-pvr2_stream_callback-casts.patch new file mode 100644 index 0000000..3e89384 --- /dev/null +++ b/patches.suse/media-pvrusb2-fix-pvr2_stream_callback-casts.patch @@ -0,0 +1,115 @@ +From 30baa4a96b23add91a87305baaeba82c4e109e1f Mon Sep 17 00:00:00 2001 +From: Arnd Bergmann +Date: Tue, 13 Feb 2024 11:04:27 +0100 +Subject: [PATCH] media: pvrusb2: fix pvr2_stream_callback casts +Git-commit: 30baa4a96b23add91a87305baaeba82c4e109e1f +Patch-mainline: v6.9-rc1 +References: git-fixes + +clang-16 complains about a control flow integrity (KCFI) issue in pvrusb2, +which casts three different prototypes into pvr2_stream_callback: + +drivers/media/usb/pvrusb2/pvrusb2-v4l2.c:1070:30: error: cast from 'void (*)(struct pvr2_v4l2_fh *)' to 'pvr2_stream_callback' (aka 'void (*)(void *)') converts to incompatible function type [-Werror,-Wcast-function-type-strict] + 1070 | pvr2_stream_set_callback(sp,(pvr2_stream_callback)pvr2_v4l2_notify,fh); + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +drivers/media/usb/pvrusb2/pvrusb2-context.c:110:6: error: cast from 'void (*)(struct pvr2_context *)' to 'void (*)(void *)' converts to incompatible function type [-Werror,-Wcast-function-type-strict] + 110 | (void (*)(void *))pvr2_context_notify, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +drivers/media/usb/pvrusb2/pvrusb2-dvb.c:152:6: error: cast from 'void (*)(struct pvr2_dvb_adapter *)' to 'pvr2_stream_callback' (aka 'void (*)(void *)') converts to incompatible function type [-Werror,-Wcast-function-type-strict] + 152 | (pvr2_stream_callback) pvr2_dvb_notify, adap); + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Change the functions to actually take a void* argument so the cast is no longer +needed. + +Fixes: bb8ce9d9143c ("V4L/DVB (7682): pvrusb2-dvb: finish up stream & buffer handling") +Signed-off-by: Arnd Bergmann +Signed-off-by: Hans Verkuil +Acked-by: Takashi Iwai + +--- + drivers/media/usb/pvrusb2/pvrusb2-context.c | 8 ++++---- + drivers/media/usb/pvrusb2/pvrusb2-dvb.c | 6 ++++-- + drivers/media/usb/pvrusb2/pvrusb2-v4l2.c | 6 ++++-- + 3 files changed, 12 insertions(+), 8 deletions(-) + +diff --git a/drivers/media/usb/pvrusb2/pvrusb2-context.c b/drivers/media/usb/pvrusb2/pvrusb2-context.c +index 1764674de98b..58f2f3ff10ee 100644 +--- a/drivers/media/usb/pvrusb2/pvrusb2-context.c ++++ b/drivers/media/usb/pvrusb2/pvrusb2-context.c +@@ -90,8 +90,10 @@ static void pvr2_context_destroy(struct pvr2_context *mp) + } + + +-static void pvr2_context_notify(struct pvr2_context *mp) ++static void pvr2_context_notify(void *ptr) + { ++ struct pvr2_context *mp = ptr; ++ + pvr2_context_set_notify(mp,!0); + } + +@@ -106,9 +108,7 @@ static void pvr2_context_check(struct pvr2_context *mp) + pvr2_trace(PVR2_TRACE_CTXT, + "pvr2_context %p (initialize)", mp); + /* Finish hardware initialization */ +- if (pvr2_hdw_initialize(mp->hdw, +- (void (*)(void *))pvr2_context_notify, +- mp)) { ++ if (pvr2_hdw_initialize(mp->hdw, pvr2_context_notify, mp)) { + mp->video_stream.stream = + pvr2_hdw_get_video_stream(mp->hdw); + /* Trigger interface initialization. By doing this +diff --git a/drivers/media/usb/pvrusb2/pvrusb2-dvb.c b/drivers/media/usb/pvrusb2/pvrusb2-dvb.c +index 6dd6c5a18251..3610139fb9ad 100644 +--- a/drivers/media/usb/pvrusb2/pvrusb2-dvb.c ++++ b/drivers/media/usb/pvrusb2/pvrusb2-dvb.c +@@ -84,8 +84,10 @@ static int pvr2_dvb_feed_thread(void *data) + return stat; + } + +-static void pvr2_dvb_notify(struct pvr2_dvb_adapter *adap) ++static void pvr2_dvb_notify(void *ptr) + { ++ struct pvr2_dvb_adapter *adap = ptr; ++ + wake_up(&adap->buffer_wait_data); + } + +@@ -145,7 +147,7 @@ static int pvr2_dvb_stream_do_start(struct pvr2_dvb_adapter *adap) + } + + pvr2_stream_set_callback(pvr->video_stream.stream, +- (pvr2_stream_callback) pvr2_dvb_notify, adap); ++ pvr2_dvb_notify, adap); + + ret = pvr2_stream_set_buffer_count(stream, PVR2_DVB_BUFFER_COUNT); + if (ret < 0) return ret; +diff --git a/drivers/media/usb/pvrusb2/pvrusb2-v4l2.c b/drivers/media/usb/pvrusb2/pvrusb2-v4l2.c +index d195bd6a2248..d608b793fa84 100644 +--- a/drivers/media/usb/pvrusb2/pvrusb2-v4l2.c ++++ b/drivers/media/usb/pvrusb2/pvrusb2-v4l2.c +@@ -1033,8 +1033,10 @@ static int pvr2_v4l2_open(struct file *file) + } + + +-static void pvr2_v4l2_notify(struct pvr2_v4l2_fh *fhp) ++static void pvr2_v4l2_notify(void *ptr) + { ++ struct pvr2_v4l2_fh *fhp = ptr; ++ + wake_up(&fhp->wait_data); + } + +@@ -1067,7 +1069,7 @@ static int pvr2_v4l2_iosetup(struct pvr2_v4l2_fh *fh) + + hdw = fh->channel.mc_head->hdw; + sp = fh->pdi->stream->stream; +- pvr2_stream_set_callback(sp,(pvr2_stream_callback)pvr2_v4l2_notify,fh); ++ pvr2_stream_set_callback(sp, pvr2_v4l2_notify, fh); + pvr2_hdw_set_stream_type(hdw,fh->pdi->config); + if ((ret = pvr2_hdw_set_streaming(hdw,!0)) < 0) return ret; + return pvr2_ioread_set_enabled(fh->rhp,!0); +-- +2.43.0 + diff --git a/patches.suse/media-pvrusb2-fix-uaf-in-pvr2_context_set_notify.patch b/patches.suse/media-pvrusb2-fix-uaf-in-pvr2_context_set_notify.patch new file mode 100644 index 0000000..a336c0d --- /dev/null +++ b/patches.suse/media-pvrusb2-fix-uaf-in-pvr2_context_set_notify.patch @@ -0,0 +1,75 @@ +From 0a0b79ea55de8514e1750884e5fec77f9fdd01ee Mon Sep 17 00:00:00 2001 +From: Edward Adam Davis +Date: Fri, 16 Feb 2024 15:30:47 +0800 +Subject: [PATCH] media: pvrusb2: fix uaf in pvr2_context_set_notify +Git-commit: 0a0b79ea55de8514e1750884e5fec77f9fdd01ee +Patch-mainline: v6.9-rc1 +References: git-fixes + +[Syzbot reported] +Bug: KASAN: slab-use-after-free in pvr2_context_set_notify+0x2c4/0x310 drivers/media/usb/pvrusb2/pvrusb2-context.c:35 +Read of size 4 at addr ffff888113aeb0d8 by task kworker/1:1/26 + +Cpu: 1 PID: 26 Comm: kworker/1:1 Not tainted 6.8.0-rc1-syzkaller-00046-gf1a27f081c1f #0 +Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/25/2024 +Workqueue: usb_hub_wq hub_event +Call Trace: + + __dump_stack lib/dump_stack.c:88 [inline] + dump_stack_lvl+0xd9/0x1b0 lib/dump_stack.c:106 + print_address_description mm/kasan/report.c:377 [inline] + print_report+0xc4/0x620 mm/kasan/report.c:488 + kasan_report+0xda/0x110 mm/kasan/report.c:601 + pvr2_context_set_notify+0x2c4/0x310 drivers/media/usb/pvrusb2/pvrusb2-context.c:35 + pvr2_context_notify drivers/media/usb/pvrusb2/pvrusb2-context.c:95 [inline] + pvr2_context_disconnect+0x94/0xb0 drivers/media/usb/pvrusb2/pvrusb2-context.c:272 + +Freed by task 906: +kasan_save_stack+0x33/0x50 mm/kasan/common.c:47 +kasan_save_track+0x14/0x30 mm/kasan/common.c:68 +kasan_save_free_info+0x3f/0x60 mm/kasan/generic.c:640 +poison_slab_object mm/kasan/common.c:241 [inline] +__kasan_slab_free+0x106/0x1b0 mm/kasan/common.c:257 +kasan_slab_free include/linux/kasan.h:184 [inline] +slab_free_hook mm/slub.c:2121 [inline] +slab_free mm/slub.c:4299 [inline] +kfree+0x105/0x340 mm/slub.c:4409 +pvr2_context_check drivers/media/usb/pvrusb2/pvrusb2-context.c:137 [inline] +pvr2_context_thread_func+0x69d/0x960 drivers/media/usb/pvrusb2/pvrusb2-context.c:158 + +[Analyze] +Task A set disconnect_flag = !0, which resulted in Task B's condition being met +and releasing mp, leading to this issue. + +[Fix] +Place the disconnect_flag assignment operation after all code in pvr2_context_disconnect() +to avoid this issue. + +Reported-and-tested-by: syzbot+ce750e124675d4599449@syzkaller.appspotmail.com +Fixes: e5be15c63804 ("V4L/DVB (7711): pvrusb2: Fix race on module unload") +Signed-off-by: Edward Adam Davis +Signed-off-by: Hans Verkuil +Acked-by: Takashi Iwai + +--- + drivers/media/usb/pvrusb2/pvrusb2-context.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/media/usb/pvrusb2/pvrusb2-context.c b/drivers/media/usb/pvrusb2/pvrusb2-context.c +index 58f2f3ff10ee..73c95ba2328a 100644 +--- a/drivers/media/usb/pvrusb2/pvrusb2-context.c ++++ b/drivers/media/usb/pvrusb2/pvrusb2-context.c +@@ -267,9 +267,9 @@ static void pvr2_context_exit(struct pvr2_context *mp) + void pvr2_context_disconnect(struct pvr2_context *mp) + { + pvr2_hdw_disconnect(mp->hdw); +- mp->disconnect_flag = !0; + if (!pvr2_context_shutok()) + pvr2_context_notify(mp); ++ mp->disconnect_flag = !0; + } + + +-- +2.43.0 + diff --git a/patches.suse/media-pvrusb2-remove-redundant-NULL-check.patch b/patches.suse/media-pvrusb2-remove-redundant-NULL-check.patch new file mode 100644 index 0000000..f44dafc --- /dev/null +++ b/patches.suse/media-pvrusb2-remove-redundant-NULL-check.patch @@ -0,0 +1,41 @@ +From 95ac1210fb2753f968ebce0730d4fbc553c2a3dc Mon Sep 17 00:00:00 2001 +From: Daniil Dulov +Date: Sun, 11 Feb 2024 07:07:25 -0800 +Subject: [PATCH] media: pvrusb2: remove redundant NULL check +Git-commit: 95ac1210fb2753f968ebce0730d4fbc553c2a3dc +Patch-mainline: v6.9-rc1 +References: git-fixes + +Pointer dip->stream cannot be NULL due to a shift, thus remove redundant +NULL check. + +Found by Linux Verification Center (linuxtesting.org) with SVACE. + +Fixes: c74e0062684b ("V4L/DVB (5059): Pvrusb2: Be smarter about mode restoration") +Signed-off-by: Daniil Dulov +Signed-off-by: Hans Verkuil +Acked-by: Takashi Iwai + +--- + drivers/media/usb/pvrusb2/pvrusb2-v4l2.c | 5 ----- + 1 file changed, 5 deletions(-) + +diff --git a/drivers/media/usb/pvrusb2/pvrusb2-v4l2.c b/drivers/media/usb/pvrusb2/pvrusb2-v4l2.c +index c04ab7258d64..d195bd6a2248 100644 +--- a/drivers/media/usb/pvrusb2/pvrusb2-v4l2.c ++++ b/drivers/media/usb/pvrusb2/pvrusb2-v4l2.c +@@ -1198,11 +1198,6 @@ static void pvr2_v4l2_dev_init(struct pvr2_v4l2_dev *dip, + dip->minor_type = pvr2_v4l_type_video; + nr_ptr = video_nr; + caps |= V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_AUDIO; +- if (!dip->stream) { +- pr_err(KBUILD_MODNAME +- ": Failed to set up pvrusb2 v4l video dev due to missing stream instance\n"); +- return; +- } + break; + case VFL_TYPE_VBI: + dip->config = pvr2_config_vbi; +-- +2.43.0 + diff --git a/patches.suse/media-sun8i-di-Fix-chroma-difference-threshold.patch b/patches.suse/media-sun8i-di-Fix-chroma-difference-threshold.patch new file mode 100644 index 0000000..de6aac1 --- /dev/null +++ b/patches.suse/media-sun8i-di-Fix-chroma-difference-threshold.patch @@ -0,0 +1,36 @@ +From 856525e8db272b0ce6d9c6e6c2eeb97892b485a6 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 16 Dec 2023 14:34:22 +0100 +Subject: [PATCH] media: sun8i-di: Fix chroma difference threshold +Git-commit: 856525e8db272b0ce6d9c6e6c2eeb97892b485a6 +Patch-mainline: v6.9-rc1 +References: git-fixes + +While there is no good explanation what this value does, vendor driver +uses value 31 for it. Align driver with it. + +Fixes: a4260ea49547 ("media: sun4i: Add H3 deinterlace driver") +Signed-off-by: Jernej Skrabec +Signed-off-by: Hans Verkuil +Acked-by: Takashi Iwai + +--- + drivers/media/platform/sunxi/sun8i-di/sun8i-di.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/media/platform/sunxi/sun8i-di/sun8i-di.c b/drivers/media/platform/sunxi/sun8i-di/sun8i-di.c +index 5d58a5e78137..a1c35a2b68ed 100644 +--- a/drivers/media/platform/sunxi/sun8i-di/sun8i-di.c ++++ b/drivers/media/platform/sunxi/sun8i-di/sun8i-di.c +@@ -304,7 +304,7 @@ static void deinterlace_init(struct deinterlace_dev *dev) + + deinterlace_clr_set_bits(dev, DEINTERLACE_CHROMA_DIFF, + DEINTERLACE_CHROMA_DIFF_TH_MSK, +- DEINTERLACE_CHROMA_DIFF_TH(5)); ++ DEINTERLACE_CHROMA_DIFF_TH(31)); + } + + static inline struct deinterlace_ctx *deinterlace_file2ctx(struct file *file) +-- +2.43.0 + diff --git a/patches.suse/media-sun8i-di-Fix-coefficient-writes.patch b/patches.suse/media-sun8i-di-Fix-coefficient-writes.patch new file mode 100644 index 0000000..5a460b7 --- /dev/null +++ b/patches.suse/media-sun8i-di-Fix-coefficient-writes.patch @@ -0,0 +1,102 @@ +From 794b581f8c6eb7b60fe468ccb96dd3cd38ff779f Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 16 Dec 2023 14:34:20 +0100 +Subject: [PATCH] media: sun8i-di: Fix coefficient writes +Git-commit: 794b581f8c6eb7b60fe468ccb96dd3cd38ff779f +Patch-mainline: v6.9-rc1 +References: git-fixes + +Currently coefficients are applied only once, since they don't change. +However, this is done before enable bit is set and thus it doesn't get +applied properly. + +Fix that by applying coefficients after enable bit is set. While this +means that it will be done evey time, it doesn't bring much time +penalty. + +Fixes: a4260ea49547 ("media: sun4i: Add H3 deinterlace driver") +Signed-off-by: Jernej Skrabec +Signed-off-by: Hans Verkuil +Acked-by: Takashi Iwai + +--- + .../media/platform/sunxi/sun8i-di/sun8i-di.c | 42 +++++++++---------- + 1 file changed, 21 insertions(+), 21 deletions(-) + +diff --git a/drivers/media/platform/sunxi/sun8i-di/sun8i-di.c b/drivers/media/platform/sunxi/sun8i-di/sun8i-di.c +index 954fabec27f6..26f6964996f2 100644 +--- a/drivers/media/platform/sunxi/sun8i-di/sun8i-di.c ++++ b/drivers/media/platform/sunxi/sun8i-di/sun8i-di.c +@@ -66,6 +66,7 @@ static void deinterlace_device_run(void *priv) + struct vb2_v4l2_buffer *src, *dst; + unsigned int hstep, vstep; + dma_addr_t addr; ++ int i; + + src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); + dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); +@@ -160,6 +161,26 @@ static void deinterlace_device_run(void *priv) + deinterlace_write(dev, DEINTERLACE_CH1_HORZ_FACT, hstep); + deinterlace_write(dev, DEINTERLACE_CH1_VERT_FACT, vstep); + ++ /* neutral filter coefficients */ ++ deinterlace_set_bits(dev, DEINTERLACE_FRM_CTRL, ++ DEINTERLACE_FRM_CTRL_COEF_ACCESS); ++ readl_poll_timeout(dev->base + DEINTERLACE_STATUS, val, ++ val & DEINTERLACE_STATUS_COEF_STATUS, 2, 40); ++ ++ for (i = 0; i < 32; i++) { ++ deinterlace_write(dev, DEINTERLACE_CH0_HORZ_COEF0 + i * 4, ++ DEINTERLACE_IDENTITY_COEF); ++ deinterlace_write(dev, DEINTERLACE_CH0_VERT_COEF + i * 4, ++ DEINTERLACE_IDENTITY_COEF); ++ deinterlace_write(dev, DEINTERLACE_CH1_HORZ_COEF0 + i * 4, ++ DEINTERLACE_IDENTITY_COEF); ++ deinterlace_write(dev, DEINTERLACE_CH1_VERT_COEF + i * 4, ++ DEINTERLACE_IDENTITY_COEF); ++ } ++ ++ deinterlace_clr_set_bits(dev, DEINTERLACE_FRM_CTRL, ++ DEINTERLACE_FRM_CTRL_COEF_ACCESS, 0); ++ + deinterlace_clr_set_bits(dev, DEINTERLACE_FIELD_CTRL, + DEINTERLACE_FIELD_CTRL_FIELD_CNT_MSK, + DEINTERLACE_FIELD_CTRL_FIELD_CNT(ctx->field)); +@@ -248,7 +269,6 @@ static irqreturn_t deinterlace_irq(int irq, void *data) + static void deinterlace_init(struct deinterlace_dev *dev) + { + u32 val; +- int i; + + deinterlace_write(dev, DEINTERLACE_BYPASS, + DEINTERLACE_BYPASS_CSC); +@@ -285,26 +305,6 @@ static void deinterlace_init(struct deinterlace_dev *dev) + deinterlace_clr_set_bits(dev, DEINTERLACE_CHROMA_DIFF, + DEINTERLACE_CHROMA_DIFF_TH_MSK, + DEINTERLACE_CHROMA_DIFF_TH(5)); +- +- /* neutral filter coefficients */ +- deinterlace_set_bits(dev, DEINTERLACE_FRM_CTRL, +- DEINTERLACE_FRM_CTRL_COEF_ACCESS); +- readl_poll_timeout(dev->base + DEINTERLACE_STATUS, val, +- val & DEINTERLACE_STATUS_COEF_STATUS, 2, 40); +- +- for (i = 0; i < 32; i++) { +- deinterlace_write(dev, DEINTERLACE_CH0_HORZ_COEF0 + i * 4, +- DEINTERLACE_IDENTITY_COEF); +- deinterlace_write(dev, DEINTERLACE_CH0_VERT_COEF + i * 4, +- DEINTERLACE_IDENTITY_COEF); +- deinterlace_write(dev, DEINTERLACE_CH1_HORZ_COEF0 + i * 4, +- DEINTERLACE_IDENTITY_COEF); +- deinterlace_write(dev, DEINTERLACE_CH1_VERT_COEF + i * 4, +- DEINTERLACE_IDENTITY_COEF); +- } +- +- deinterlace_clr_set_bits(dev, DEINTERLACE_FRM_CTRL, +- DEINTERLACE_FRM_CTRL_COEF_ACCESS, 0); + } + + static inline struct deinterlace_ctx *deinterlace_file2ctx(struct file *file) +-- +2.43.0 + diff --git a/patches.suse/media-sun8i-di-Fix-power-on-off-sequences.patch b/patches.suse/media-sun8i-di-Fix-power-on-off-sequences.patch new file mode 100644 index 0000000..58d947a --- /dev/null +++ b/patches.suse/media-sun8i-di-Fix-power-on-off-sequences.patch @@ -0,0 +1,88 @@ +From cff104e33bad38f4b2c8d58816a7accfaa2879f9 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 16 Dec 2023 14:34:21 +0100 +Subject: [PATCH] media: sun8i-di: Fix power on/off sequences +Git-commit: cff104e33bad38f4b2c8d58816a7accfaa2879f9 +Patch-mainline: v6.9-rc1 +References: git-fixes + +According to user manual, reset line should be deasserted before clocks +are enabled. Also fix power down sequence to be reverse of that. + +Fixes: a4260ea49547 ("media: sun4i: Add H3 deinterlace driver") +Signed-off-by: Jernej Skrabec +Signed-off-by: Hans Verkuil +Acked-by: Takashi Iwai + +--- + .../media/platform/sunxi/sun8i-di/sun8i-di.c | 25 ++++++++++--------- + 1 file changed, 13 insertions(+), 12 deletions(-) + +diff --git a/drivers/media/platform/sunxi/sun8i-di/sun8i-di.c b/drivers/media/platform/sunxi/sun8i-di/sun8i-di.c +index 26f6964996f2..5d58a5e78137 100644 +--- a/drivers/media/platform/sunxi/sun8i-di/sun8i-di.c ++++ b/drivers/media/platform/sunxi/sun8i-di/sun8i-di.c +@@ -929,11 +929,18 @@ static int deinterlace_runtime_resume(struct device *device) + return ret; + } + ++ ret = reset_control_deassert(dev->rstc); ++ if (ret) { ++ dev_err(dev->dev, "Failed to apply reset\n"); ++ ++ goto err_exclusive_rate; ++ } ++ + ret = clk_prepare_enable(dev->bus_clk); + if (ret) { + dev_err(dev->dev, "Failed to enable bus clock\n"); + +- goto err_exclusive_rate; ++ goto err_rst; + } + + ret = clk_prepare_enable(dev->mod_clk); +@@ -950,23 +957,16 @@ static int deinterlace_runtime_resume(struct device *device) + goto err_mod_clk; + } + +- ret = reset_control_deassert(dev->rstc); +- if (ret) { +- dev_err(dev->dev, "Failed to apply reset\n"); +- +- goto err_ram_clk; +- } +- + deinterlace_init(dev); + + return 0; + +-err_ram_clk: +- clk_disable_unprepare(dev->ram_clk); + err_mod_clk: + clk_disable_unprepare(dev->mod_clk); + err_bus_clk: + clk_disable_unprepare(dev->bus_clk); ++err_rst: ++ reset_control_assert(dev->rstc); + err_exclusive_rate: + clk_rate_exclusive_put(dev->mod_clk); + +@@ -977,11 +977,12 @@ static int deinterlace_runtime_suspend(struct device *device) + { + struct deinterlace_dev *dev = dev_get_drvdata(device); + +- reset_control_assert(dev->rstc); +- + clk_disable_unprepare(dev->ram_clk); + clk_disable_unprepare(dev->mod_clk); + clk_disable_unprepare(dev->bus_clk); ++ ++ reset_control_assert(dev->rstc); ++ + clk_rate_exclusive_put(dev->mod_clk); + + return 0; +-- +2.43.0 + diff --git a/patches.suse/media-ttpci-fix-two-memleaks-in-budget_av_attach.patch b/patches.suse/media-ttpci-fix-two-memleaks-in-budget_av_attach.patch new file mode 100644 index 0000000..acc2498 --- /dev/null +++ b/patches.suse/media-ttpci-fix-two-memleaks-in-budget_av_attach.patch @@ -0,0 +1,52 @@ +From d0b07f712bf61e1a3cf23c87c663791c42e50837 Mon Sep 17 00:00:00 2001 +From: Zhipeng Lu +Date: Wed, 21 Feb 2024 13:17:04 +0800 +Subject: [PATCH] media: ttpci: fix two memleaks in budget_av_attach +Git-commit: d0b07f712bf61e1a3cf23c87c663791c42e50837 +Patch-mainline: v6.9-rc1 +References: git-fixes + +When saa7146_register_device and saa7146_vv_init fails, budget_av_attach +should free the resources it allocates, like the error-handling of +ttpci_budget_init does. Besides, there are two fixme comment refers to +such deallocations. + +Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") +Signed-off-by: Zhipeng Lu +Signed-off-by: Hans Verkuil +Acked-by: Takashi Iwai + +--- + drivers/media/pci/ttpci/budget-av.c | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +diff --git a/drivers/media/pci/ttpci/budget-av.c b/drivers/media/pci/ttpci/budget-av.c +index 230b104a7cdf..a47c5850ef87 100644 +--- a/drivers/media/pci/ttpci/budget-av.c ++++ b/drivers/media/pci/ttpci/budget-av.c +@@ -1463,7 +1463,8 @@ static int budget_av_attach(struct saa7146_dev *dev, struct saa7146_pci_extensio + budget_av->has_saa7113 = 1; + err = saa7146_vv_init(dev, &vv_data); + if (err != 0) { +- /* fixme: proper cleanup here */ ++ ttpci_budget_deinit(&budget_av->budget); ++ kfree(budget_av); + ERR("cannot init vv subsystem\n"); + return err; + } +@@ -1472,9 +1473,10 @@ static int budget_av_attach(struct saa7146_dev *dev, struct saa7146_pci_extensio + vv_data.vid_ops.vidioc_s_input = vidioc_s_input; + + if ((err = saa7146_register_device(&budget_av->vd, dev, "knc1", VFL_TYPE_VIDEO))) { +- /* fixme: proper cleanup here */ +- ERR("cannot register capture v4l2 device\n"); + saa7146_vv_release(dev); ++ ttpci_budget_deinit(&budget_av->budget); ++ kfree(budget_av); ++ ERR("cannot register capture v4l2 device\n"); + return err; + } + +-- +2.43.0 + diff --git a/patches.suse/media-usbtv-Remove-useless-locks-in-usbtv_video_free.patch b/patches.suse/media-usbtv-Remove-useless-locks-in-usbtv_video_free.patch new file mode 100644 index 0000000..5e654d9 --- /dev/null +++ b/patches.suse/media-usbtv-Remove-useless-locks-in-usbtv_video_free.patch @@ -0,0 +1,55 @@ +From 65e6a2773d655172143cc0b927cdc89549842895 Mon Sep 17 00:00:00 2001 +From: Benjamin Gaignard +Date: Sat, 2 Mar 2024 11:37:08 +0100 +Subject: [PATCH] media: usbtv: Remove useless locks in usbtv_video_free() +Git-commit: 65e6a2773d655172143cc0b927cdc89549842895 +Patch-mainline: v6.9-rc1 +References: git-fixes + +Remove locks calls in usbtv_video_free() because +are useless and may led to a deadlock as reported here: +https://syzkaller.appspot.com/x/bisect.txt?x=166dc872180000 +Also remove usbtv_stop() call since it will be called when +unregistering the device. + +Before 'c838530d230b' this issue would only be noticed if you +disconnect while streaming and now it is noticeable even when +disconnecting while not streaming. + +Fixes: c838530d230b ("media: media videobuf2: Be more flexible on the number of queue stored buffers") +Fixes: f3d27f34fdd7 ("[media] usbtv: Add driver for Fushicai USBTV007 video frame grabber") + +Signed-off-by: Benjamin Gaignard +Reviewed-by: Tomasz Figa +Tested-by: Hans Verkuil +Signed-off-by: Hans Verkuil +[hverkuil: fix minor spelling mistake in log message] +Acked-by: Takashi Iwai + +--- + drivers/media/usb/usbtv/usbtv-video.c | 7 ------- + 1 file changed, 7 deletions(-) + +diff --git a/drivers/media/usb/usbtv/usbtv-video.c b/drivers/media/usb/usbtv/usbtv-video.c +index 62a583040cd4..702f1c8bd2ab 100644 +--- a/drivers/media/usb/usbtv/usbtv-video.c ++++ b/drivers/media/usb/usbtv/usbtv-video.c +@@ -963,15 +963,8 @@ int usbtv_video_init(struct usbtv *usbtv) + + void usbtv_video_free(struct usbtv *usbtv) + { +- mutex_lock(&usbtv->vb2q_lock); +- mutex_lock(&usbtv->v4l2_lock); +- +- usbtv_stop(usbtv); + vb2_video_unregister_device(&usbtv->vdev); + v4l2_device_disconnect(&usbtv->v4l2_dev); + +- mutex_unlock(&usbtv->v4l2_lock); +- mutex_unlock(&usbtv->vb2q_lock); +- + v4l2_device_put(&usbtv->v4l2_dev); + } +-- +2.43.0 + diff --git a/patches.suse/media-v4l2-mem2mem-fix-a-memleak-in-v4l2_m2m_registe.patch b/patches.suse/media-v4l2-mem2mem-fix-a-memleak-in-v4l2_m2m_registe.patch new file mode 100644 index 0000000..7cbdc81 --- /dev/null +++ b/patches.suse/media-v4l2-mem2mem-fix-a-memleak-in-v4l2_m2m_registe.patch @@ -0,0 +1,48 @@ +From 8f94b49a5b5d386c038e355bef6347298aabd211 Mon Sep 17 00:00:00 2001 +From: Zhipeng Lu +Date: Thu, 1 Feb 2024 20:48:44 +0800 +Subject: [PATCH] media: v4l2-mem2mem: fix a memleak in v4l2_m2m_register_entity +Git-commit: 8f94b49a5b5d386c038e355bef6347298aabd211 +Patch-mainline: v6.9-rc1 +References: git-fixes + +The entity->name (i.e. name) is allocated in v4l2_m2m_register_entity +but isn't freed in its following error-handling paths. This patch +adds such deallocation to prevent memleak of entity->name. + +Fixes: be2fff656322 ("media: add helpers for memory-to-memory media controller") +Signed-off-by: Zhipeng Lu +Signed-off-by: Hans Verkuil +Acked-by: Takashi Iwai + +--- + drivers/media/v4l2-core/v4l2-mem2mem.c | 10 ++++++++-- + 1 file changed, 8 insertions(+), 2 deletions(-) + +diff --git a/drivers/media/v4l2-core/v4l2-mem2mem.c b/drivers/media/v4l2-core/v4l2-mem2mem.c +index 9e983176542b..75517134a5e9 100644 +--- a/drivers/media/v4l2-core/v4l2-mem2mem.c ++++ b/drivers/media/v4l2-core/v4l2-mem2mem.c +@@ -1087,11 +1087,17 @@ static int v4l2_m2m_register_entity(struct media_device *mdev, + entity->function = function; + + ret = media_entity_pads_init(entity, num_pads, pads); +- if (ret) ++ if (ret) { ++ kfree(entity->name); ++ entity->name = NULL; + return ret; ++ } + ret = media_device_register_entity(mdev, entity); +- if (ret) ++ if (ret) { ++ kfree(entity->name); ++ entity->name = NULL; + return ret; ++ } + + return 0; + } +-- +2.43.0 + diff --git a/patches.suse/media-v4l2-tpg-fix-some-memleaks-in-tpg_alloc.patch b/patches.suse/media-v4l2-tpg-fix-some-memleaks-in-tpg_alloc.patch new file mode 100644 index 0000000..0bb431d --- /dev/null +++ b/patches.suse/media-v4l2-tpg-fix-some-memleaks-in-tpg_alloc.patch @@ -0,0 +1,112 @@ +From 8cf9c5051076e0eb958f4361d50d8b0c3ee6691c Mon Sep 17 00:00:00 2001 +From: Zhipeng Lu +Date: Thu, 1 Feb 2024 20:47:53 +0800 +Subject: [PATCH] media: v4l2-tpg: fix some memleaks in tpg_alloc +Git-commit: 8cf9c5051076e0eb958f4361d50d8b0c3ee6691c +Patch-mainline: v6.9-rc1 +References: git-fixes + +In tpg_alloc, resources should be deallocated in each and every +error-handling paths, since they are allocated in for statements. +Otherwise there would be memleaks because tpg_free is called only when +tpg_alloc return 0. + +Fixes: 63881df94d3e ("[media] vivid: add the Test Pattern Generator") +Signed-off-by: Zhipeng Lu +Signed-off-by: Hans Verkuil +Acked-by: Takashi Iwai + +--- + drivers/media/common/v4l2-tpg/v4l2-tpg-core.c | 52 +++++++++++++++---- + 1 file changed, 42 insertions(+), 10 deletions(-) + +diff --git a/drivers/media/common/v4l2-tpg/v4l2-tpg-core.c b/drivers/media/common/v4l2-tpg/v4l2-tpg-core.c +index a366566f22c3..642c48e8c1f5 100644 +--- a/drivers/media/common/v4l2-tpg/v4l2-tpg-core.c ++++ b/drivers/media/common/v4l2-tpg/v4l2-tpg-core.c +@@ -113,6 +113,7 @@ int tpg_alloc(struct tpg_data *tpg, unsigned max_w) + { + unsigned pat; + unsigned plane; ++ int ret = 0; + + tpg->max_line_width = max_w; + for (pat = 0; pat < TPG_MAX_PAT_LINES; pat++) { +@@ -121,14 +122,18 @@ int tpg_alloc(struct tpg_data *tpg, unsigned max_w) + + tpg->lines[pat][plane] = + vzalloc(array3_size(max_w, 2, pixelsz)); +- if (!tpg->lines[pat][plane]) +- return -ENOMEM; ++ if (!tpg->lines[pat][plane]) { ++ ret = -ENOMEM; ++ goto free_lines; ++ } + if (plane == 0) + continue; + tpg->downsampled_lines[pat][plane] = + vzalloc(array3_size(max_w, 2, pixelsz)); +- if (!tpg->downsampled_lines[pat][plane]) +- return -ENOMEM; ++ if (!tpg->downsampled_lines[pat][plane]) { ++ ret = -ENOMEM; ++ goto free_lines; ++ } + } + } + for (plane = 0; plane < TPG_MAX_PLANES; plane++) { +@@ -136,18 +141,45 @@ int tpg_alloc(struct tpg_data *tpg, unsigned max_w) + + tpg->contrast_line[plane] = + vzalloc(array_size(pixelsz, max_w)); +- if (!tpg->contrast_line[plane]) +- return -ENOMEM; ++ if (!tpg->contrast_line[plane]) { ++ ret = -ENOMEM; ++ goto free_contrast_line; ++ } + tpg->black_line[plane] = + vzalloc(array_size(pixelsz, max_w)); +- if (!tpg->black_line[plane]) +- return -ENOMEM; ++ if (!tpg->black_line[plane]) { ++ ret = -ENOMEM; ++ goto free_contrast_line; ++ } + tpg->random_line[plane] = + vzalloc(array3_size(max_w, 2, pixelsz)); +- if (!tpg->random_line[plane]) +- return -ENOMEM; ++ if (!tpg->random_line[plane]) { ++ ret = -ENOMEM; ++ goto free_contrast_line; ++ } + } + return 0; ++ ++free_contrast_line: ++ for (plane = 0; plane < TPG_MAX_PLANES; plane++) { ++ vfree(tpg->contrast_line[plane]); ++ vfree(tpg->black_line[plane]); ++ vfree(tpg->random_line[plane]); ++ tpg->contrast_line[plane] = NULL; ++ tpg->black_line[plane] = NULL; ++ tpg->random_line[plane] = NULL; ++ } ++free_lines: ++ for (pat = 0; pat < TPG_MAX_PAT_LINES; pat++) ++ for (plane = 0; plane < TPG_MAX_PLANES; plane++) { ++ vfree(tpg->lines[pat][plane]); ++ tpg->lines[pat][plane] = NULL; ++ if (plane == 0) ++ continue; ++ vfree(tpg->downsampled_lines[pat][plane]); ++ tpg->downsampled_lines[pat][plane] = NULL; ++ } ++ return ret; + } + EXPORT_SYMBOL_GPL(tpg_alloc); + +-- +2.43.0 + diff --git a/patches.suse/media-xc4000-Fix-atomicity-violation-in-xc4000_get_f.patch b/patches.suse/media-xc4000-Fix-atomicity-violation-in-xc4000_get_f.patch new file mode 100644 index 0000000..aee10fe --- /dev/null +++ b/patches.suse/media-xc4000-Fix-atomicity-violation-in-xc4000_get_f.patch @@ -0,0 +1,79 @@ +From 36d503ad547d1c75758a6fcdbec2806f1b6aeb41 Mon Sep 17 00:00:00 2001 +From: Gui-Dong Han <2045gemini@gmail.com> +Date: Fri, 22 Dec 2023 13:50:30 +0800 +Subject: [PATCH] media: xc4000: Fix atomicity violation in xc4000_get_frequency +Git-commit: 36d503ad547d1c75758a6fcdbec2806f1b6aeb41 +Patch-mainline: v6.9-rc1 +References: git-fixes + +In xc4000_get_frequency(): + *freq = priv->freq_hz + priv->freq_offset; +The code accesses priv->freq_hz and priv->freq_offset without holding any +lock. + +In xc4000_set_params(): + // Code that updates priv->freq_hz and priv->freq_offset + ... + +xc4000_get_frequency() and xc4000_set_params() may execute concurrently, +risking inconsistent reads of priv->freq_hz and priv->freq_offset. Since +these related data may update during reading, it can result in incorrect +frequency calculation, leading to atomicity violations. + +This possible bug is found by an experimental static analysis tool +developed by our team, BassCheck[1]. This tool analyzes the locking APIs +to extract function pairs that can be concurrently executed, and then +analyzes the instructions in the paired functions to identify possible +concurrency bugs including data races and atomicity violations. The above +possible bug is reported when our tool analyzes the source code of +Linux 6.2. + +To address this issue, it is proposed to add a mutex lock pair in +xc4000_get_frequency() to ensure atomicity. With this patch applied, our +tool no longer reports the possible bug, with the kernel configuration +allyesconfig for x86_64. Due to the lack of associated hardware, we cannot +test the patch in runtime testing, and just verify it according to the +code logic. + +[1] https://sites.google.com/view/basscheck/ + +Fixes: 4c07e32884ab ("[media] xc4000: Fix get_frequency()") +Cc: stable@vger.kernel.org +Reported-by: BassCheck +Signed-off-by: Gui-Dong Han <2045gemini@gmail.com> +Signed-off-by: Hans Verkuil +Acked-by: Takashi Iwai + +--- + drivers/media/tuners/xc4000.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/media/tuners/xc4000.c b/drivers/media/tuners/xc4000.c +index 57ded9ff3f04..29bc63021c5a 100644 +--- a/drivers/media/tuners/xc4000.c ++++ b/drivers/media/tuners/xc4000.c +@@ -1515,10 +1515,10 @@ static int xc4000_get_frequency(struct dvb_frontend *fe, u32 *freq) + { + struct xc4000_priv *priv = fe->tuner_priv; + ++ mutex_lock(&priv->lock); + *freq = priv->freq_hz + priv->freq_offset; + + if (debug) { +- mutex_lock(&priv->lock); + if ((priv->cur_fw.type + & (BASE | FM | DTV6 | DTV7 | DTV78 | DTV8)) == BASE) { + u16 snr = 0; +@@ -1529,8 +1529,8 @@ static int xc4000_get_frequency(struct dvb_frontend *fe, u32 *freq) + return 0; + } + } +- mutex_unlock(&priv->lock); + } ++ mutex_unlock(&priv->lock); + + dprintk(1, "%s()\n", __func__); + +-- +2.43.0 + diff --git a/patches.suse/mmc-mmci-stm32-fix-DMA-API-overlapping-mappings-warn.patch b/patches.suse/mmc-mmci-stm32-fix-DMA-API-overlapping-mappings-warn.patch new file mode 100644 index 0000000..65cc94b --- /dev/null +++ b/patches.suse/mmc-mmci-stm32-fix-DMA-API-overlapping-mappings-warn.patch @@ -0,0 +1,111 @@ +From 6b1ba3f9040be5efc4396d86c9752cdc564730be Mon Sep 17 00:00:00 2001 +From: Christophe Kerello +Date: Wed, 7 Feb 2024 15:39:51 +0100 +Subject: [PATCH] mmc: mmci: stm32: fix DMA API overlapping mappings warning +Git-commit: 6b1ba3f9040be5efc4396d86c9752cdc564730be +Patch-mainline: v6.8-rc7 +References: git-fixes + +Turning on CONFIG_DMA_API_DEBUG_SG results in the following warning: + +Dma-api: mmci-pl18x 48220000.mmc: cacheline tracking EEXIST, +overlapping mappings aren't supported +Warning: CPU: 1 PID: 51 at kernel/dma/debug.c:568 +add_dma_entry+0x234/0x2f4 +Modules linked in: +Cpu: 1 PID: 51 Comm: kworker/1:2 Not tainted 6.1.28 #1 +Hardware name: STMicroelectronics STM32MP257F-EV1 Evaluation Board (DT) +Workqueue: events_freezable mmc_rescan +Call trace: +add_dma_entry+0x234/0x2f4 +debug_dma_map_sg+0x198/0x350 +__dma_map_sg_attrs+0xa0/0x110 +dma_map_sg_attrs+0x10/0x2c +sdmmc_idma_prep_data+0x80/0xc0 +mmci_prep_data+0x38/0x84 +mmci_start_data+0x108/0x2dc +mmci_request+0xe4/0x190 +__mmc_start_request+0x68/0x140 +mmc_start_request+0x94/0xc0 +mmc_wait_for_req+0x70/0x100 +mmc_send_tuning+0x108/0x1ac +sdmmc_execute_tuning+0x14c/0x210 +mmc_execute_tuning+0x48/0xec +mmc_sd_init_uhs_card.part.0+0x208/0x464 +mmc_sd_init_card+0x318/0x89c +mmc_attach_sd+0xe4/0x180 +mmc_rescan+0x244/0x320 + +DMA API debug brings to light leaking dma-mappings as dma_map_sg and +dma_unmap_sg are not correctly balanced. + +If an error occurs in mmci_cmd_irq function, only mmci_dma_error +function is called and as this API is not managed on stm32 variant, +dma_unmap_sg is never called in this error path. + +Signed-off-by: Christophe Kerello +Fixes: 46b723dd867d ("mmc: mmci: add stm32 sdmmc variant") +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/r/20240207143951.938144-1-christophe.kerello@foss.st.com +Signed-off-by: Ulf Hansson +Acked-by: Takashi Iwai + +--- + drivers/mmc/host/mmci_stm32_sdmmc.c | 24 ++++++++++++++++++++++++ + 1 file changed, 24 insertions(+) + +diff --git a/drivers/mmc/host/mmci_stm32_sdmmc.c b/drivers/mmc/host/mmci_stm32_sdmmc.c +index 35067e1e6cd8..f5da7f9baa52 100644 +--- a/drivers/mmc/host/mmci_stm32_sdmmc.c ++++ b/drivers/mmc/host/mmci_stm32_sdmmc.c +@@ -225,6 +225,8 @@ static int sdmmc_idma_start(struct mmci_host *host, unsigned int *datactrl) + struct scatterlist *sg; + int i; + ++ host->dma_in_progress = true; ++ + if (!host->variant->dma_lli || data->sg_len == 1 || + idma->use_bounce_buffer) { + u32 dma_addr; +@@ -263,9 +265,30 @@ static int sdmmc_idma_start(struct mmci_host *host, unsigned int *datactrl) + return 0; + } + ++static void sdmmc_idma_error(struct mmci_host *host) ++{ ++ struct mmc_data *data = host->data; ++ struct sdmmc_idma *idma = host->dma_priv; ++ ++ if (!dma_inprogress(host)) ++ return; ++ ++ writel_relaxed(0, host->base + MMCI_STM32_IDMACTRLR); ++ host->dma_in_progress = false; ++ data->host_cookie = 0; ++ ++ if (!idma->use_bounce_buffer) ++ dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, ++ mmc_get_dma_dir(data)); ++} ++ + static void sdmmc_idma_finalize(struct mmci_host *host, struct mmc_data *data) + { ++ if (!dma_inprogress(host)) ++ return; ++ + writel_relaxed(0, host->base + MMCI_STM32_IDMACTRLR); ++ host->dma_in_progress = false; + + if (!data->host_cookie) + sdmmc_idma_unprep_data(host, data, 0); +@@ -676,6 +699,7 @@ static struct mmci_host_ops sdmmc_variant_ops = { + .dma_setup = sdmmc_idma_setup, + .dma_start = sdmmc_idma_start, + .dma_finalize = sdmmc_idma_finalize, ++ .dma_error = sdmmc_idma_error, + .set_clkreg = mmci_sdmmc_set_clkreg, + .set_pwrreg = mmci_sdmmc_set_pwrreg, + .busy_complete = sdmmc_busy_complete, +-- +2.43.0 + diff --git a/patches.suse/mmc-mmci-stm32-use-a-buffer-for-unaligned-DMA-reques.patch b/patches.suse/mmc-mmci-stm32-use-a-buffer-for-unaligned-DMA-reques.patch new file mode 100644 index 0000000..676ca8e --- /dev/null +++ b/patches.suse/mmc-mmci-stm32-use-a-buffer-for-unaligned-DMA-reques.patch @@ -0,0 +1,183 @@ +From 970dc9c11a17994ab878016b536612ab00d1441d Mon Sep 17 00:00:00 2001 +From: Yann Gautier +Date: Mon, 28 Mar 2022 16:51:14 +0200 +Subject: [PATCH] mmc: mmci: stm32: use a buffer for unaligned DMA requests +Git-commit: 970dc9c11a17994ab878016b536612ab00d1441d +Patch-mainline: v5.19-rc1 +References: git-fixes + +In SDIO mode, the sg list for requests can be unaligned with what the +STM32 SDMMC internal DMA can support. In that case, instead of failing, +use a temporary bounce buffer to copy from/to the sg list. +This buffer is limited to 1MB. But for that we need to also limit +max_req_size to 1MB. It has not shown any throughput penalties for +SD-cards or eMMC. + +Signed-off-by: Yann Gautier +Link: https://lore.kernel.org/r/20220328145114.334577-1-yann.gautier@foss.st.com +Signed-off-by: Ulf Hansson +Acked-by: Takashi Iwai + +--- + drivers/mmc/host/mmci_stm32_sdmmc.c | 88 +++++++++++++++++++++++------ + 1 file changed, 71 insertions(+), 17 deletions(-) + +diff --git a/drivers/mmc/host/mmci_stm32_sdmmc.c b/drivers/mmc/host/mmci_stm32_sdmmc.c +index 4566d7fc9055..60bca78a72b1 100644 +--- a/drivers/mmc/host/mmci_stm32_sdmmc.c ++++ b/drivers/mmc/host/mmci_stm32_sdmmc.c +@@ -43,6 +43,9 @@ struct sdmmc_lli_desc { + struct sdmmc_idma { + dma_addr_t sg_dma; + void *sg_cpu; ++ dma_addr_t bounce_dma_addr; ++ void *bounce_buf; ++ bool use_bounce_buffer; + }; + + struct sdmmc_dlyb { +@@ -54,6 +57,8 @@ struct sdmmc_dlyb { + static int sdmmc_idma_validate_data(struct mmci_host *host, + struct mmc_data *data) + { ++ struct sdmmc_idma *idma = host->dma_priv; ++ struct device *dev = mmc_dev(host->mmc); + struct scatterlist *sg; + int i; + +@@ -61,41 +66,69 @@ static int sdmmc_idma_validate_data(struct mmci_host *host, + * idma has constraints on idmabase & idmasize for each element + * excepted the last element which has no constraint on idmasize + */ ++ idma->use_bounce_buffer = false; + for_each_sg(data->sg, sg, data->sg_len - 1, i) { + if (!IS_ALIGNED(sg->offset, sizeof(u32)) || + !IS_ALIGNED(sg->length, SDMMC_IDMA_BURST)) { +- dev_err(mmc_dev(host->mmc), ++ dev_dbg(mmc_dev(host->mmc), + "unaligned scatterlist: ofst:%x length:%d\n", + data->sg->offset, data->sg->length); +- return -EINVAL; ++ goto use_bounce_buffer; + } + } + + if (!IS_ALIGNED(sg->offset, sizeof(u32))) { +- dev_err(mmc_dev(host->mmc), ++ dev_dbg(mmc_dev(host->mmc), + "unaligned last scatterlist: ofst:%x length:%d\n", + data->sg->offset, data->sg->length); +- return -EINVAL; ++ goto use_bounce_buffer; + } + ++ return 0; ++ ++use_bounce_buffer: ++ if (!idma->bounce_buf) { ++ idma->bounce_buf = dmam_alloc_coherent(dev, ++ host->mmc->max_req_size, ++ &idma->bounce_dma_addr, ++ GFP_KERNEL); ++ if (!idma->bounce_buf) { ++ dev_err(dev, "Unable to map allocate DMA bounce buffer.\n"); ++ return -ENOMEM; ++ } ++ } ++ ++ idma->use_bounce_buffer = true; ++ + return 0; + } + + static int _sdmmc_idma_prep_data(struct mmci_host *host, + struct mmc_data *data) + { +- int n_elem; ++ struct sdmmc_idma *idma = host->dma_priv; + +- n_elem = dma_map_sg(mmc_dev(host->mmc), +- data->sg, +- data->sg_len, +- mmc_get_dma_dir(data)); ++ if (idma->use_bounce_buffer) { ++ if (data->flags & MMC_DATA_WRITE) { ++ unsigned int xfer_bytes = data->blksz * data->blocks; + +- if (!n_elem) { +- dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n"); +- return -EINVAL; ++ sg_copy_to_buffer(data->sg, data->sg_len, ++ idma->bounce_buf, xfer_bytes); ++ dma_wmb(); ++ } ++ } else { ++ int n_elem; ++ ++ n_elem = dma_map_sg(mmc_dev(host->mmc), ++ data->sg, ++ data->sg_len, ++ mmc_get_dma_dir(data)); ++ ++ if (!n_elem) { ++ dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n"); ++ return -EINVAL; ++ } + } +- + return 0; + } + +@@ -112,8 +145,19 @@ static int sdmmc_idma_prep_data(struct mmci_host *host, + static void sdmmc_idma_unprep_data(struct mmci_host *host, + struct mmc_data *data, int err) + { +- dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, +- mmc_get_dma_dir(data)); ++ struct sdmmc_idma *idma = host->dma_priv; ++ ++ if (idma->use_bounce_buffer) { ++ if (data->flags & MMC_DATA_READ) { ++ unsigned int xfer_bytes = data->blksz * data->blocks; ++ ++ sg_copy_from_buffer(data->sg, data->sg_len, ++ idma->bounce_buf, xfer_bytes); ++ } ++ } else { ++ dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, ++ mmc_get_dma_dir(data)); ++ } + } + + static int sdmmc_idma_setup(struct mmci_host *host) +@@ -137,6 +181,8 @@ static int sdmmc_idma_setup(struct mmci_host *host) + host->mmc->max_segs = SDMMC_LLI_BUF_LEN / + sizeof(struct sdmmc_lli_desc); + host->mmc->max_seg_size = host->variant->stm32_idmabsize_mask; ++ ++ host->mmc->max_req_size = SZ_1M; + } else { + host->mmc->max_segs = 1; + host->mmc->max_seg_size = host->mmc->max_req_size; +@@ -154,8 +200,16 @@ static int sdmmc_idma_start(struct mmci_host *host, unsigned int *datactrl) + struct scatterlist *sg; + int i; + +- if (!host->variant->dma_lli || data->sg_len == 1) { +- writel_relaxed(sg_dma_address(data->sg), ++ if (!host->variant->dma_lli || data->sg_len == 1 || ++ idma->use_bounce_buffer) { ++ u32 dma_addr; ++ ++ if (idma->use_bounce_buffer) ++ dma_addr = idma->bounce_dma_addr; ++ else ++ dma_addr = sg_dma_address(data->sg); ++ ++ writel_relaxed(dma_addr, + host->base + MMCI_STM32_IDMABASE0R); + writel_relaxed(MMCI_STM32_IDMAEN, + host->base + MMCI_STM32_IDMACTRLR); +-- +2.43.0 + diff --git a/patches.suse/mtd-maps-physmap-core-fix-flash-size-larger-than-32-.patch b/patches.suse/mtd-maps-physmap-core-fix-flash-size-larger-than-32-.patch new file mode 100644 index 0000000..b5d6b47 --- /dev/null +++ b/patches.suse/mtd-maps-physmap-core-fix-flash-size-larger-than-32-.patch @@ -0,0 +1,39 @@ +From 3884f03edd34887514a0865a80769cd5362d5c3b Mon Sep 17 00:00:00 2001 +From: Baruch Siach +Date: Thu, 8 Feb 2024 12:34:18 +0200 +Subject: [PATCH] mtd: maps: physmap-core: fix flash size larger than 32-bit +Git-commit: 3884f03edd34887514a0865a80769cd5362d5c3b +Patch-mainline: v6.9-rc1 +References: git-fixes + +mtd-ram can potentially be larger than 4GB. get_bitmask_order() uses +fls() that is not guaranteed to work with values larger than 32-bit. +Specifically on aarch64 fls() returns 0 when all 32 LSB bits are clear. +Use fls64() instead. + +Fixes: ba32ce95cbd987 ("mtd: maps: Merge gpio-addr-flash.c into physmap-core.c") +Signed-off-by: Baruch Siach +Signed-off-by: Miquel Raynal +Link: https://lore.kernel.org/linux-mtd/9fbf3664ce00f8b07867f1011834015f21d162a5.1707388458.git.baruch@tkos.co.il +Acked-by: Takashi Iwai + +--- + drivers/mtd/maps/physmap-core.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/mtd/maps/physmap-core.c b/drivers/mtd/maps/physmap-core.c +index 746a27d15d44..96eb2e782c38 100644 +--- a/drivers/mtd/maps/physmap-core.c ++++ b/drivers/mtd/maps/physmap-core.c +@@ -518,7 +518,7 @@ static int physmap_flash_probe(struct platform_device *dev) + if (!info->maps[i].phys) + info->maps[i].phys = res->start; + +- info->win_order = get_bitmask_order(resource_size(res)) - 1; ++ info->win_order = fls64(resource_size(res)) - 1; + info->maps[i].size = BIT(info->win_order + + (info->gpios ? + info->gpios->ndescs : 0)); +-- +2.43.0 + diff --git a/patches.suse/mtd-rawnand-lpc32xx_mlc-fix-irq-handler-prototype.patch b/patches.suse/mtd-rawnand-lpc32xx_mlc-fix-irq-handler-prototype.patch new file mode 100644 index 0000000..2953e87 --- /dev/null +++ b/patches.suse/mtd-rawnand-lpc32xx_mlc-fix-irq-handler-prototype.patch @@ -0,0 +1,52 @@ +From 347b828882e6334690e7003ce5e2fe5f233dc508 Mon Sep 17 00:00:00 2001 +From: Arnd Bergmann +Date: Tue, 13 Feb 2024 11:00:09 +0100 +Subject: [PATCH] mtd: rawnand: lpc32xx_mlc: fix irq handler prototype +Git-commit: 347b828882e6334690e7003ce5e2fe5f233dc508 +Patch-mainline: v6.9-rc1 +References: git-fixes + +clang-16 warns about mismatched function prototypes: + +drivers/mtd/nand/raw/lpc32xx_mlc.c:783:29: error: cast from 'irqreturn_t (*)(int, struct lpc32xx_nand_host *)' (aka 'enum irqreturn (*)(int, struct lpc32xx_nand_host *)') to 'irq_handler_t' (aka 'enum irqreturn (*)(int, void *)') converts to incompatible function type [-Werror,-Wcast-function-type-strict] + +Change the interrupt handler to the normal way of just passing +a void* pointer and converting it inside the function.. + +Fixes: 70f7cb78ec53 ("mtd: add LPC32xx MLC NAND driver") +Signed-off-by: Arnd Bergmann +Signed-off-by: Miquel Raynal +Link: https://lore.kernel.org/linux-mtd/20240213100146.455811-1-arnd@kernel.org +Acked-by: Takashi Iwai + +--- + drivers/mtd/nand/raw/lpc32xx_mlc.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +diff --git a/drivers/mtd/nand/raw/lpc32xx_mlc.c b/drivers/mtd/nand/raw/lpc32xx_mlc.c +index 488fd452611a..677fcb03f9be 100644 +--- a/drivers/mtd/nand/raw/lpc32xx_mlc.c ++++ b/drivers/mtd/nand/raw/lpc32xx_mlc.c +@@ -303,8 +303,9 @@ static int lpc32xx_nand_device_ready(struct nand_chip *nand_chip) + return 0; + } + +-static irqreturn_t lpc3xxx_nand_irq(int irq, struct lpc32xx_nand_host *host) ++static irqreturn_t lpc3xxx_nand_irq(int irq, void *data) + { ++ struct lpc32xx_nand_host *host = data; + uint8_t sr; + + /* Clear interrupt flag by reading status */ +@@ -780,7 +781,7 @@ static int lpc32xx_nand_probe(struct platform_device *pdev) + goto release_dma_chan; + } + +- if (request_irq(host->irq, (irq_handler_t)&lpc3xxx_nand_irq, ++ if (request_irq(host->irq, &lpc3xxx_nand_irq, + IRQF_TRIGGER_HIGH, DRV_NAME, host)) { + dev_err(&pdev->dev, "Error requesting NAND IRQ\n"); + res = -ENXIO; +-- +2.43.0 + diff --git a/patches.suse/mtd-rawnand-meson-fix-scrambling-mode-value-in-comma.patch b/patches.suse/mtd-rawnand-meson-fix-scrambling-mode-value-in-comma.patch new file mode 100644 index 0000000..0803605 --- /dev/null +++ b/patches.suse/mtd-rawnand-meson-fix-scrambling-mode-value-in-comma.patch @@ -0,0 +1,39 @@ +From ef6f463599e16924cdd02ce5056ab52879dc008c Mon Sep 17 00:00:00 2001 +From: Arseniy Krasnov +Date: Sun, 11 Feb 2024 00:45:51 +0300 +Subject: [PATCH] mtd: rawnand: meson: fix scrambling mode value in command macro +Git-commit: ef6f463599e16924cdd02ce5056ab52879dc008c +Patch-mainline: v6.9-rc1 +References: git-fixes + +Scrambling mode is enabled by value (1 << 19). NFC_CMD_SCRAMBLER_ENABLE +is already (1 << 19), so there is no need to shift it again in CMDRWGEN +macro. + +Signed-off-by: Arseniy Krasnov +Cc: +Fixes: 8fae856c5350 ("mtd: rawnand: meson: add support for Amlogic NAND flash controller") +Signed-off-by: Miquel Raynal +Link: https://lore.kernel.org/linux-mtd/20240210214551.441610-1-avkrasnov@salutedevices.com +Acked-by: Takashi Iwai + +--- + drivers/mtd/nand/raw/meson_nand.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson_nand.c +index cdb58aca59c0..2a96a87cf79c 100644 +--- a/drivers/mtd/nand/raw/meson_nand.c ++++ b/drivers/mtd/nand/raw/meson_nand.c +@@ -63,7 +63,7 @@ + #define CMDRWGEN(cmd_dir, ran, bch, short_mode, page_size, pages) \ + ( \ + (cmd_dir) | \ +- ((ran) << 19) | \ ++ (ran) | \ + ((bch) << 14) | \ + ((short_mode) << 13) | \ + (((page_size) & 0x7f) << 6) | \ +-- +2.43.0 + diff --git a/patches.suse/net-lan78xx-fix-runtime-PM-count-underflow-on-link-s.patch b/patches.suse/net-lan78xx-fix-runtime-PM-count-underflow-on-link-s.patch new file mode 100644 index 0000000..d9d6f79 --- /dev/null +++ b/patches.suse/net-lan78xx-fix-runtime-PM-count-underflow-on-link-s.patch @@ -0,0 +1,45 @@ +From 1eecc7ab82c42133b748e1895275942a054a7f67 Mon Sep 17 00:00:00 2001 +From: Oleksij Rempel +Date: Wed, 28 Feb 2024 13:45:17 +0100 +Subject: [PATCH] net: lan78xx: fix runtime PM count underflow on link stop +Git-commit: 1eecc7ab82c42133b748e1895275942a054a7f67 +Patch-mainline: v6.8 +References: git-fixes + +Current driver has some asymmetry in the runtime PM calls. On lan78xx_open() +it will call usb_autopm_get() and unconditionally usb_autopm_put(). And +on lan78xx_stop() it will call only usb_autopm_put(). So far, it was +working only because this driver do not activate autosuspend by default, +so it was visible only by warning "Runtime PM usage count underflow!". + +Since, with current driver, we can't use runtime PM with active link, +execute lan78xx_open()->usb_autopm_put() only in error case. Otherwise, +keep ref counting high as long as interface is open. + +Fixes: 55d7de9de6c3 ("Microchip's LAN7800 family USB 2/3 to 10/100/1000 Ethernet device driver") +Signed-off-by: Oleksij Rempel +Reviewed-by: Jiri Pirko +Signed-off-by: David S. Miller +Acked-by: Takashi Iwai + +--- + drivers/net/usb/lan78xx.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/usb/lan78xx.c b/drivers/net/usb/lan78xx.c +index ba6c8ac2a736..d2aa2c5b1989 100644 +--- a/drivers/net/usb/lan78xx.c ++++ b/drivers/net/usb/lan78xx.c +@@ -3135,7 +3135,8 @@ static int lan78xx_open(struct net_device *net) + done: + mutex_unlock(&dev->dev_mutex); + +- usb_autopm_put_interface(dev->intf); ++ if (ret < 0) ++ usb_autopm_put_interface(dev->intf); + + return ret; + } +-- +2.43.0 + diff --git a/patches.suse/watchdog-stm32_iwdg-initialize-default-timeout.patch b/patches.suse/watchdog-stm32_iwdg-initialize-default-timeout.patch new file mode 100644 index 0000000..9509152 --- /dev/null +++ b/patches.suse/watchdog-stm32_iwdg-initialize-default-timeout.patch @@ -0,0 +1,59 @@ +From dbd7c0088b7f44aa0b9276ed3449df075a7b5b54 Mon Sep 17 00:00:00 2001 +From: Ben Wolsieffer +Date: Wed, 28 Feb 2024 13:27:23 -0500 +Subject: [PATCH] watchdog: stm32_iwdg: initialize default timeout +Git-commit: dbd7c0088b7f44aa0b9276ed3449df075a7b5b54 +Patch-mainline: v6.9-rc1 +References: git-fixes + +The driver never sets a default timeout value, therefore it is +initialized to zero. When CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED is +enabled, the watchdog is started during probe. The kernel is supposed to +automatically ping the watchdog from this point until userspace takes +over, but this does not happen if the configured timeout is zero. A zero +timeout causes watchdog_need_worker() to return false, so the heartbeat +worker does not run and the system therefore resets soon after the +driver is probed. + +This patch fixes this by setting an arbitrary non-zero default timeout. +The default could be read from the hardware instead, but I didn't see +any reason to add this complexity. + +This has been tested on an STM32F746. + +Fixes: 85fdc63fe256 ("drivers: watchdog: stm32_iwdg: set WDOG_HW_RUNNING at probe") +Signed-off-by: Ben Wolsieffer +Reviewed-by: Guenter Roeck +Link: https://lore.kernel.org/r/20240228182723.12855-1-ben.wolsieffer@hefring.com +Signed-off-by: Guenter Roeck +Signed-off-by: Wim Van Sebroeck +Acked-by: Takashi Iwai + +--- + drivers/watchdog/stm32_iwdg.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/watchdog/stm32_iwdg.c b/drivers/watchdog/stm32_iwdg.c +index d9fd50df9802..5404e0387620 100644 +--- a/drivers/watchdog/stm32_iwdg.c ++++ b/drivers/watchdog/stm32_iwdg.c +@@ -20,6 +20,8 @@ + #include + #include + ++#define DEFAULT_TIMEOUT 10 ++ + /* IWDG registers */ + #define IWDG_KR 0x00 /* Key register */ + #define IWDG_PR 0x04 /* Prescaler Register */ +@@ -248,6 +250,7 @@ static int stm32_iwdg_probe(struct platform_device *pdev) + wdd->parent = dev; + wdd->info = &stm32_iwdg_info; + wdd->ops = &stm32_iwdg_ops; ++ wdd->timeout = DEFAULT_TIMEOUT; + wdd->min_timeout = DIV_ROUND_UP((RLR_MIN + 1) * PR_MIN, wdt->rate); + wdd->max_hw_heartbeat_ms = ((RLR_MAX + 1) * wdt->data->max_prescaler * + 1000) / wdt->rate; +-- +2.43.0 + diff --git a/series.conf b/series.conf index ec99c1f..f67039f 100644 --- a/series.conf +++ b/series.conf @@ -25360,6 +25360,7 @@ patches.suse/mtd-rawnand-intel-fix-possible-null-ptr-deref-in-ebu.patch patches.suse/ipmi-ssif-Check-for-NULL-msg-when-handling-events-an.patch patches.suse/ipmi-Fix-pr_fmt-to-avoid-compilation-issues.patch + patches.suse/mmc-mmci-stm32-use-a-buffer-for-unaligned-DMA-reques.patch patches.suse/mmc-jz4740-Apply-DMA-engine-limits-to-maximum-segmen.patch patches.suse/drivers-mmc-sdhci_am654-Add-the-quirk-to-set-TESTCD-.patch patches.suse/mmc-core-Allows-to-override-the-timeout-value-for-io.patch @@ -35773,6 +35774,7 @@ patches.suse/0283-drm-amdgpu-Use-vm-status_lock-to-protect-vm-evicted-.patch patches.suse/0284-drm-amdgpu-Use-vm-status_lock-to-protect-pt-free.patch patches.suse/0285-drm-amdgpu-Fix-amdgpu_vm_pt_free-warning.patch + patches.suse/drm-i915-gt-Use-i915_vm_put-on-ppgtt_create-error-pa.patch patches.suse/drm-meson-reorder-driver-deinit-sequence-to-fix-use-.patch patches.suse/drm-meson-explicitly-remove-aggregate-driver-at-modu.patch patches.suse/virtio-gpu-fix-shift-wrapping-bug-in-virtio_gpu_fenc.patch @@ -36762,6 +36764,7 @@ patches.suse/wwan_hwsim-fix-possible-memory-leak-in-wwan_hwsim_de.patch patches.suse/net-sched-fix-race-condition-in-qdisc_graft.patch patches.suse/net-phy-dp83822-disable-MDI-crossover-status-change-.patch + patches.suse/drm-vc4-Add-module-dependency-on-hdmi-codec.patch patches.suse/drm-vc4-hdmi-Enforce-the-minimum-rate-at-runtime_res.patch patches.suse/drm-amdgpu-set-vm_update_mode-0-as-default-for-Sienn.patch patches.suse/0436-Revert-drm-amdgpu-add-debugfs-amdgpu_reset_level.patch @@ -37073,6 +37076,7 @@ patches.suse/fuse-add-file_modified-to-fallocate.patch patches.suse/ata-pata_legacy-fix-pdc20230_set_piomode.patch patches.suse/drm-rockchip-dw_hdmi-filter-regulator-EPROBE_DEFER-e.patch + patches.suse/drm-rockchip-dsi-Clean-up-usage_mode-when-failing-to.patch patches.suse/drm-rockchip-dsi-Force-synchronous-probe.patch patches.suse/drm-rockchip-fix-fbdev-on-non-IOMMU-devices.patch patches.suse/drm-imx-Kconfig-Remove-duplicated-select-DRM_KMS_HEL.patch @@ -37217,6 +37221,7 @@ patches.suse/drm-amdgpu-disable-BACO-on-special-BEIGE_GOBY-card.patch patches.suse/0509-drm-amd-display-only-fill-dirty-rectangles-when-PSR-.patch patches.suse/drm-vc4-Fix-missing-platform_unregister_drivers-call.patch + patches.suse/drm-panel-orientation-quirks-Add-quirk-for-Acer-Swit.patch patches.suse/0510-drm-amdgpu-Fix-the-lpfn-checking-condition-in-drm-bu.patch patches.suse/drm-i915-dmabuf-fix-sg_table-handling-in-map_dma_buf.patch patches.suse/drm-i915-psr-Send-update-also-on-invalidate.patch @@ -38197,6 +38202,16 @@ patches.suse/drm-amdgpu-add-tmz-support-for-GC-11.0.1.patch patches.suse/drm-amdgpu-Revert-drm-amdgpu-getting-fan-speed-pwm-f.patch patches.suse/drm-amdgpu-powerplay-psm-Fix-memory-leak-in-power-st.patch + patches.suse/drm-amd-display-Check-if-link-state-is-valid.patch + patches.suse/drm-amd-display-Rework-context-change-check.patch + patches.suse/drm-amd-display-Enable-new-commit-sequence-only-for-.patch + patches.suse/drm-amd-display-Copy-DC-context-in-the-commit-stream.patch + patches.suse/drm-amd-display-Include-surface-of-unaffected-stream.patch + patches.suse/drm-amd-display-Handle-virtual-hardware-detect.patch + patches.suse/drm-amd-display-Add-function-for-validate-and-update.patch + patches.suse/drm-amd-display-Handle-seamless-boot-stream.patch + patches.suse/drm-amd-display-Update-OTG-instance-in-the-commit-st.patch + patches.suse/drm-amd-display-Avoid-ABM-when-ODM-combine-is-enable.patch patches.suse/drm-amd-display-Use-update-plane-and-stream-routine-.patch patches.suse/drm-amdkfd-introduce-dummy-cache-info-for-property-a.patch patches.suse/drm-amd-display-Remove-FPU-guards-from-the-DML-folde.patch @@ -38204,6 +38219,9 @@ patches.suse/drm-amd-display-Remove-optimization-for-VRR-updates.patch patches.suse/drm-amd-display-wait-for-vblank-during-pipe-programm.patch patches.suse/drm-amd-display-skip-commit-minimal-transition-state.patch + patches.suse/drm-amd-display-Wrong-colorimetry-workaround.patch + patches.suse/drm-amd-display-Expand-kernel-doc-for-DC.patch + patches.suse/drm-amd-display-Rework-comments-on-dc-file.patch patches.suse/drm-amdgpu-remove-deprecated-MES-version-vars.patch patches.suse/drm-amd-display-move-remaining-FPU-code-to-dml-folde.patch patches.suse/drm-amd-display-prevent-memory-leak.patch @@ -38242,7 +38260,10 @@ patches.suse/drm-radeon-Add-the-missed-acpi_put_table-to-fix-memo.patch patches.suse/drm-amdgpu-add-vram-reservation-based-on-vram_usageb.patch patches.suse/drm-amd-display-delete-the-duplicate-.set_odm_bypass.patch + patches.suse/drm-amd-display-Use-min-transition-for-all-SubVP-pla.patch + patches.suse/drm-amd-display-use-low-clocks-for-no-plane-configs.patch patches.suse/drm-amd-display-Workaround-to-increase-phantom-pipe-.patch + patches.suse/drm-amd-display-fix-unbounded-requesting-for-high-pi.patch patches.suse/drm-amd-display-revert-Disable-DRR-actions-during-st.patch patches.suse/drm-amd-display-fix-array-index-out-of-bound-error-i.patch patches.suse/amdgpu-pm-prevent-array-underflow-in-vega20_odn_edit.patch @@ -38251,6 +38272,7 @@ patches.suse/drm-amdgpu-dm-mst-Use-the-correct-topology-mgr-point.patch patches.suse/drm-amdgpu-dm-dp_mst-Don-t-grab-mst_mgr-lock-when-co.patch patches.suse/drm-amdgpu-Add-support-for-RAS-table-at-0x40000.patch + patches.suse/drm-amd-display-fix-kernel-doc-issues-in-dc.h.patch patches.suse/drm-i915-pxp-use-instead-of-for-headers-in-include.patch patches.suse/drm-i915-ttm-never-purge-busy-objects.patch patches.suse/drm-i915-Use-_MMIO_PIPE-for-SKL_BOTTOM_COLOR.patch @@ -38310,11 +38332,13 @@ patches.suse/drm-radeon-Fix-PCI-device-refcount-leak-in-radeon_at.patch patches.suse/drm-amd-display-Use-the-largest-vready_offset-in-pip.patch patches.suse/drm-amd-display-Fix-race-condition-in-DPIA-AUX-trans.patch + patches.suse/drm-amd-display-set-per-pipe-dppclk-to-0-when-dpp-is.patch patches.suse/drm-amd-display-Fix-DTBCLK-disable-requests-and-SRC_.patch patches.suse/drm-amdgpu-Fix-PCI-device-refcount-leak-in-amdgpu_at.patch patches.suse/drm-amdkfd-Fix-memory-leakage.patch patches.suse/drm-amd-amdgpu-update-mes11-api-def.patch patches.suse/drm-amdgpu-mes11-enable-reg-active-poll.patch + patches.suse/drm-amd-display-add-FB_DAMAGE_CLIPS-support.patch patches.suse/drm-amd-display-trigger-timing-sync-only-if-TG-is-ru-5f9f97c02dd2.patch patches.suse/drm-amd-display-Add-debug-option-to-skip-PSR-CRTC-di.patch patches.suse/drm-amdgpu-enable-GFX-IP-v11.0.4-CG-support.patch @@ -40133,6 +40157,7 @@ patches.suse/drm-amd-display-save-restore-hdcp-state-when-display.patch patches.suse/drm-amd-display-phase3-mst-hdcp-for-multiple-display.patch patches.suse/drm-amd-display-Defer-DIG-FIFO-disable-after-VID-str.patch + patches.suse/drm-amd-display-fix-dc-core-dc.c-kernel-doc.patch patches.suse/drm-amd-Add-a-new-helper-for-loading-validating-micr.patch patches.suse/drm-amd-display-fix-PSR-SU-DSC-interoperability-supp.patch patches.suse/drm-amd-Load-MES-microcode-during-early_init.patch @@ -40211,6 +40236,7 @@ patches.suse/drm-amd-display-Enable-P-state-validation-checks-for.patch patches.suse/drm-amd-display-Remove-stutter-only-configurations.patch patches.suse/drm-amd-display-Update-Z8-SR-exit-enter-latencies.patch + patches.suse/drm-amd-display-clean-code-style-issues-in-dcn30_set.patch patches.suse/drm-amd-display-Disable-HUBP-DPP-PG-on-DCN314-for-no.patch patches.suse/drm-i915-Populate-encoder-devdata-for-DSI-on-icl.patch patches.suse/drm-shmem-helper-Fix-locking-for-drm_gem_shmem_get_p.patch @@ -40672,6 +40698,7 @@ patches.suse/drm-amd-pm-bump-SMU-13.0.4-driver_if-header-version.patch patches.suse/drm-amd-pm-Fix-sienna-cichlid-incorrect-OD-volage-af.patch patches.suse/drm-amdkfd-fix-potential-kgd_mem-UAFs.patch + patches.suse/drm-amd-display-Write-to-correct-dirty_rect.patch patches.suse/drm-amdgpu-vcn-Disable-indirect-SRAM-on-Vangogh-brok.patch patches.suse/drm-amd-display-Remove-OTG-DIV-register-write-for-Vi.patch patches.suse/drm-amd-display-Do-not-set-DRR-on-pipe-Commit.patch @@ -41219,8 +41246,10 @@ patches.suse/drm-vgem-add-missing-mutex_destroy.patch patches.suse/0001-drm-vmwgfx-Remove-the-duplicate-bo_free-function.patch patches.suse/0001-drm-vmwgfx-Rename-vmw_buffer_object-to-vmw_bo.patch + patches.suse/Revert-drm-vc4-hdmi-Enforce-the-minimum-rate-at-runt.patch patches.suse/drm-displayid-add-displayid_get_header-and-check-bou.patch patches.suse/drm-probe-helper-Cancel-previous-job-before-starting.patch + patches.suse/drm-ttm-Don-t-print-error-message-if-eviction-was-in.patch patches.suse/drm-bridge-adv7533-Fix-adv7533_mode_valid-for-adv753.patch patches.suse/drm-rockchip-dw_hdmi-cleanup-drm-encoder-during-unbi.patch patches.suse/drm-i915-lvds-Use-REG_BIT-co.patch @@ -41232,17 +41261,20 @@ patches.suse/drm-amd-display-Simplify-same-effect-if-else-blocks.patch patches.suse/drm-amd-display-Add-minimum-Z8-residency-debug-optio.patch patches.suse/drm-amd-display-Update-minimum-stutter-residency-for.patch + patches.suse/drm-amd-display-Keep-PHY-active-for-dp-config.patch patches.suse/drm-amd-display-Enable-HostVM-based-on-rIOMMU-active.patch patches.suse/drm-amd-display-Ensure-vmin-and-vmax-adjust-for-DCE.patch patches.suse/drm-amd-display-Use-dc_update_planes_and_stream.patch patches.suse/drm-amd-display-Use-DC_LOG_DC-in-the-trasform-pixel-.patch patches.suse/drm-amd-display-Add-wrapper-to-call-planes-and-strea.patch patches.suse/drm-amd-display-Ensure-that-planes-are-in-the-same-o.patch + patches.suse/Revert-drm-amdgpu-display-change-pipe-policy-for-DCN.patch patches.suse/drm-i915-tc-Fix-TC-port-link-ref-init-for-DP-MST-dur.patch patches.suse/drm-i915-tc-Fix-system-resume-MST-mode-restore-for-D.patch patches.suse/drm-rcar-du-Fix-a-NULL-vs-IS_ERR-bug.patch patches.suse/drm-amd-display-dc-dce60-Makefile-Fix-previous-attem.patch patches.suse/drm-amd-display-Implement-workaround-for-writing-to-.patch + patches.suse/Revert-drm-amdgpu-display-change-pipe-policy-for-DCN-27dd79c.patch patches.suse/drm-amd-amdgpu-limit-one-queue-per-gang.patch patches.suse/drm-amdgpu-Remove-second-moot-switch-to-set-EEPROM-I.patch patches.suse/drm-amdgpu-Return-from-switch-early-for-EEPROM-I2C-a.patch @@ -42104,6 +42136,7 @@ patches.suse/drm-amdgpu-fix-Null-pointer-dereference-error-in-amd.patch patches.suse/drm-amd-pm-Fix-power-context-allocation-in-SMU13.patch patches.suse/drm-amd-pm-conditionally-disable-pcie-lane-switching.patch + patches.suse/drm-amd-display-add-ODM-case-when-looking-for-first-.patch patches.suse/drm-radeon-fix-race-condition-UAF-in-radeon_gem_set_.patch patches.suse/drm-amdgpu-fix-xclk-freq-on-CHIP_STONEY.patch patches.suse/drm-amdgpu-change-reserved-vram-info-print.patch @@ -42483,6 +42516,7 @@ patches.suse/drm-vram-helper-fix-function-names-in-vram-helper-do.patch patches.suse/drm-sun4i_tcon-use-devm_clk_get_enabled-in-sun4i_tco.patch patches.suse/drm-panel-sharp-ls043t1le01-adjust-mode-settings.patch + patches.suse/drm-panel-boe-tv101wum-nl6-Fine-tune-the-panel-power.patch patches.suse/drm-Add-fixed-point-helper-to-get-rounded-integer-va.patch patches.suse/drm-bridge-tc358767-Switch-to-devm-MIPI-DSI-helpers.patch patches.suse/drm-bridge-anx7625-Prevent-endless-probe-loop.patch @@ -42491,6 +42525,7 @@ patches.suse/drm-rcar-du-remove-R-Car-H3-ES1.-workarounds.patch patches.suse/drm-i915-Relocate-intel_atomic_setup_scalers.patch patches.suse/drm-i915-sdvo-stop-caching-has_hdmi_monitor-in-struc.patch + patches.suse/drm-amd-display-Add-FAMS-validation-before-trying-to.patch patches.suse/drm-amd-display-Add-logging-for-display-MALL-refresh.patch patches.suse/radeon-avoid-double-free-in-ci_dpm_init.patch patches.suse/drm-amdgpu-fix-calltrace-warning-in-amddrm_buddy_fin.patch @@ -42498,14 +42533,20 @@ patches.suse/drm-radeon-Fix-integer-overflow-in-radeon_cs_parser_.patch patches.suse/drm-amdgpu-Fix-integer-overflow-in-amdgpu_cs_pass1.patch patches.suse/drm-amdgpu-fix-memory-leak-in-mes-self-test.patch + patches.suse/drm-amd-display-Restore-rptr-wptr-for-DMCUB-as-worka.patch + patches.suse/drm-amd-display-update-extended-blank-for-dcn314-onw.patch patches.suse/drm-amd-display-Fix-a-test-CalculatePrefetchSchedule.patch patches.suse/drm-amd-display-Fix-a-test-dml32_rq_dlg_get_rq_reg.patch patches.suse/drm-amdkfd-Fix-potential-deallocation-of-previously-.patch + patches.suse/drm-amd-display-Fix-possible-underflow-for-displays-.patch patches.suse/drm-amdkfd-Flush-TLB-after-unmapping-for-GFX-v9.4.3.patch patches.suse/drm-amd-display-drop-redundant-memset-in-get_availab.patch patches.suse/drm-amdgpu-Validate-VM-ioctl-flags.patch patches.suse/drm-amd-display-Fix-artifacting-on-eDP-panels-when-e.patch + patches.suse/drm-amd-display-Revert-vblank-change-that-causes-nul.patch + patches.suse/drm-amd-display-Fix-possible-underflow-for-displays--de23118.patch patches.suse/drm-amd-display-Apply-60us-prefetch-for-DCFCLK-300Mh.patch + patches.suse/drm-amd-display-Update-correct-DCN314-register-heade.patch patches.suse/drm-radeon-fix-possible-division-by-zero-errors.patch patches.suse/drm-amdgpu-keep-irq-count-in-amdgpu_irq_disable_all.patch patches.suse/drm-amd-display-fix-seamless-odm-transitions.patch @@ -42832,10 +42873,15 @@ patches.suse/drm-amd-pm-update-the-LC_L1_INACTIVITY-setting-to-ad.patch patches.suse/drm-amd-Disable-PSR-SU-on-Parade-0803-TCON.patch patches.suse/drm-amd-pm-add-abnormal-fan-detection-for-smu-13.0.0.patch + patches.suse/drm-amd-display-perform-a-bounds-check-before-fillin.patch patches.suse/drm-amdgpu-fix-number-of-fence-calculations.patch patches.suse/drm-amd-Don-t-try-to-enable-secure-display-TA-multip.patch patches.suse/drm-amd-display-Correct-DMUB_FW_VERSION-macro.patch + patches.suse/drm-amd-display-Set-minimum-requirement-for-using-PS.patch + patches.suse/drm-amd-display-Set-minimum-requirement-for-using-PS-cd2e31a.patch + patches.suse/Revert-drm-amd-Disable-PSR-SU-on-Parade-0803-TCON.patch patches.suse/Revert-drm-amd-display-edp-do-not-add-non-edid-timin.patch + patches.suse/drm-amd-display-Fix-the-delta-clamping-for-shaper-LU.patch patches.suse/drm-amd-display-Remove-Phantom-Pipe-Check-When-Calcu.patch patches.suse/drm-amd-display-Add-monitor-specific-edid-quirk.patch patches.suse/drm-amd-pm-expose-swctf-threshold-setting-for-legacy.patch @@ -42911,6 +42957,7 @@ patches.suse/drm-ttm-fix-bulk_move-corruption-when-adding-a-entry.patch patches.suse/drm-ttm-fix-warning-that-we-shouldn-t-mix-and.patch patches.suse/drm-bridge-ti-sn65dsi86-Fix-auxiliary-bus-lifetime.patch + patches.suse/drm-ttm-Don-t-leak-a-resource-on-eviction-error.patch patches.suse/drm-ttm-Don-t-leak-a-resource-on-swapout-move-error.patch patches.suse/drm-panel-simple-Add-Powertip-PH800480T013-drm_displ.patch patches.suse/drm-ttm-never-consider-pinned-BOs-for-eviction-swap.patch @@ -42987,9 +43034,12 @@ patches.suse/dma-buf-dma-resv-Stop-leaking-on-krealloc-failure.patch patches.suse/drm-amdgpu-vkms-relax-timer-deactivation-by-hrtimer_.patch patches.suse/drm-amd-display-only-accept-async-flips-for-fast-upd.patch + patches.suse/drm-amdgpu-pm-make-gfxclock-consistent-for-sienna-ci.patch + patches.suse/drm-amdgpu-pm-make-mclk-consistent-for-smu-13.0.7.patch patches.suse/drm-amd-display-Add-polling-method-to-handle-MST-rep.patch patches.suse/drm-amd-display-check-TG-is-non-null-before-checking.patch patches.suse/drm-amd-display-Disable-MPC-split-by-default-on-spec.patch + patches.suse/drm-amd-display-Prevent-vtotal-from-being-set-to-0.patch patches.suse/drm-amd-display-Keep-PHY-active-for-DP-displays-on-D.patch patches.suse/drm-atomic-Fix-potential-use-after-free-in-nonblocki.patch patches.suse/fbdev-imxfb-warn-about-invalid-left-right-margin.patch @@ -43056,6 +43106,9 @@ patches.suse/drm-i915-dpt-Use-shmem-for-dpt-objects.patch patches.suse/drm-i915-Fix-an-error-handling-path-in-igt_write_hug.patch patches.suse/drm-amd-Fix-an-error-handling-mistake-in-psp_sw_init.patch + patches.suse/drm-amd-smu-use-AverageGfxclkFrequency-to-replace-pr.patch + patches.suse/drm-amd-display-Guard-DCN31-PHYD32CLK-logic-against-.patch + patches.suse/drm-amd-display-Exit-idle-optimizations-before-attem.patch patches.suse/drm-amd-display-Unlock-on-error-path-in-dm_handle_ms.patch patches.suse/drm-msm-dpu-drop-enum-dpu_core_perf_data_bus_id.patch patches.suse/drm-msm-adreno-Fix-snapshot-BINDLESS_DATA-size.patch @@ -43207,6 +43260,7 @@ patches.suse/drm-shmem-helper-Reset-vma-vm_ops-before-calling-dma.patch patches.suse/drm-amd-Disable-S-G-for-APUs-when-64GB-or-more-host-.patch patches.suse/drm-amd-pm-skip-the-RLC-stop-when-S0i3-suspend-for-S.patch + patches.suse/drm-amdgpu-Match-against-exact-bootloader-status.patch patches.suse/drm-amd-display-check-attr-flag-before-set-cursor-de.patch patches.suse/drm-amdgpu-fix-possible-UAF-in-amdgpu_cs_pass1.patch patches.suse/PCI-acpiphp-Use-pci_assign_unassigned_bridge_resourc.patch @@ -43249,6 +43303,7 @@ patches.suse/drm-amdgpu-pm-fix-throttle_status-for-other-than-MP1.patch patches.suse/drm-amdgpu-skip-fence-GFX-interrupts-disable-enable-.patch patches.suse/drm-amd-flush-any-delayed-gfxoff-on-suspend-entry.patch + patches.suse/Revert-Revert-drm-amdgpu-display-change-pipe-policy-.patch patches.suse/drm-qxl-fix-UAF-on-handle-creation.patch patches.suse/virtio-net-set-queues-after-driver_ok.patch patches.suse/net-phy-fix-IRQ-based-wake-on-lan-over-hibernate-pow.patch @@ -43472,19 +43527,24 @@ patches.suse/quota-fix-dqput-to-follow-the-guarantees-dquot_srcu-.patch patches.suse/xfs-fix-agf_fllast-when-repairing-an-empty-AGFL.patch patches.suse/drm-bridge-tc358764-Fix-debug-print-parameter-order.patch + patches.suse/drm-bridge-tc358762-Instruct-DSI-host-to-generate-HS.patch patches.suse/drm-mxsfb-Disable-overlay-plane-in-mxsfb_plane_overl.patch patches.suse/backlight-bd6107-Compare-against-struct-fb_info.devi.patch patches.suse/backlight-gpio_backlight-Compare-against-struct-fb_i.patch patches.suse/backlight-lv5207lp-Compare-against-struct-fb_info.de.patch patches.suse/fbdev-ep93xx-fb-Do-not-assign-to-struct-fb_info.dev.patch patches.suse/drm-ast-Fix-DRAM-init-on-AST2200.patch + patches.suse/drm-edid-Add-quirk-for-OSVR-HDK-2.0.patch patches.suse/drm-bridge-anx7625-Use-common-macros-for-DP-power-se.patch patches.suse/drm-bridge-anx7625-Use-common-macros-for-HDCP-capabi.patch patches.suse/drm-adv7511-Fix-low-refresh-rate-register-for-ADV753.patch patches.suse/drm-bridge-anx7625-Drop-device-lock-before-drm_helpe.patch patches.suse/drm-amd-display-Do-not-set-drr-on-pipe-commit.patch patches.suse/drm-amdgpu-avoid-integer-overflow-warning-in-amdgpu_.patch + patches.suse/drm-amd-display-dc.h-eliminate-kernel-doc-warnings.patch patches.suse/drm-amd-amdgpu-Fix-warnings-in-amdgpu-amdgpu_display.patch + patches.suse/drm-amd-display-Fix-underflow-issue-on-175hz-timing.patch + patches.suse/drm-amdgpu-Update-min-to-min_t-in-amdgpu_info_ioctl.patch patches.suse/drm-xlnx-zynqmp_dpsub-Add-missing-check-for-dma_set_.patch patches.suse/drm-tegra-dpaux-Fix-incorrect-return-value-of-platfo.patch patches.suse/drm-atomic-helper-Update-reference-to-drm_crtc_force.patch @@ -43494,10 +43554,15 @@ patches.suse/drm-repaper-Reduce-temporary-buffer-size-in-repaper_.patch patches.suse/drm-bridge-fix-Wunused-const-variable-warning.patch patches.suse/drm-panel-simple-Add-missing-connector-type-and-pixe.patch + patches.suse/drm-exynos-fix-a-possible-null-pointer-dereference-d.patch patches.suse/drm-mediatek-Remove-freeing-not-dynamic-allocated-me.patch patches.suse/drm-mediatek-Fix-dereference-before-null-check.patch patches.suse/drm-mediatek-Fix-potential-memory-leak-if-vmap-fail.patch patches.suse/drm-amd-pm-fix-variable-dereferenced-issue-in-amdgpu.patch + patches.suse/drm-amd-display-ensure-async-flips-are-only-accepted.patch + patches.suse/drm-amd-display-Fix-a-bug-when-searching-for-insert_.patch + patches.suse/drm-amd-display-Use-DTBCLK-as-refclk-instead-of-DPRE.patch + patches.suse/drm-amd-display-Blocking-invalid-420-modes-on-HDMI-T.patch patches.suse/drm-etnaviv-fix-dumping-of-active-MMU-context.patch patches.suse/drm-amdgpu-Add-I2C-EEPROM-support-on-smu-v13_0_6.patch patches.suse/drm-msm-Update-dev-core-dump-to-not-print-backwards.patch @@ -43842,6 +43907,7 @@ patches.suse/drm-amd-display-register-edp_backlight_control-for-D.patch patches.suse/drm-amd-display-Add-smu-write-msg-id-fail-retry-proc.patch patches.suse/drm-amd-display-Remove-wait-while-locked.patch + patches.suse/drm-amd-display-always-switch-off-ODM-before-committ.patch patches.suse/drm-amd-display-enable-cursor-degamma-for-DCN3-DRM-l.patch patches.suse/drm-amd-display-prevent-potential-division-by-zero-e.patch patches.suse/arm64-csum-Fix-OoB-access-in-IP-checksum-code-for-ne.patch @@ -43888,6 +43954,7 @@ patches.suse/efi-unaccepted-Use-ACPI-reclaim-memory-for-unaccepted-memory-table.patch patches.suse/drm-gm12u320-Fix-the-timeout-usage-for-usb_bulk_msg.patch patches.suse/drm-amd-display-fix-the-white-screen-issue-when-64GB.patch + patches.suse/Revert-drm-amd-Disable-S-G-for-APUs-when-64GB-or-mor.patch patches.suse/drm-amd-display-Don-t-check-registers-if-using-AUX-B.patch patches.suse/drm-amdgpu-soc21-don-t-remap-HDP-registers-for-SR-IO.patch patches.suse/drm-amdgpu-nbio4.3-set-proper-rmmio_remap.reg_offset.patch @@ -44160,7 +44227,9 @@ patches.suse/0002-x86-sev-Check-IOBM-for-IOIO-exceptions-from-user-spa.patch patches.suse/0003-x86-sev-Check-for-user-space-IOIO-pointing-to-kernel.patch patches.suse/drm-amdgpu-Reserve-fences-for-VM-update.patch + patches.suse/drm-panel-Move-AUX-B116XW03-out-of-panel-edp-back-to.patch patches.suse/drm-ttm-Reorder-sys-manager-cleanup-step.patch + patches.suse/drm-amdgpu-Unset-context-priority-is-now-invalid.patch patches.suse/drm-i915-Retry-gtt-fault-when-out-of-fence-registers.patch patches.suse/drm-mediatek-Correctly-free-sg_table-in-gem-prime-vm.patch patches.suse/ALSA-hda-relatek-Enable-Mute-LED-on-HP-Laptop-15s-fq.patch @@ -44365,6 +44434,7 @@ patches.suse/drm-panel-fix-a-possible-null-pointer-dereference.patch patches.suse/drm-panel-panel-tpo-tpg110-fix-a-possible-null-point.patch patches.suse/gpu-host1x-Correct-allocated-size-for-contexts.patch + patches.suse/drm-i915-Add-missing-CCS-documentation.patch patches.suse/drm-radeon-possible-buffer-overflow.patch patches.suse/drm-amd-display-remove-useless-check-in-should_enabl.patch patches.suse/drm-amdkfd-fix-some-race-conditions-in-vram-buffer-a.patch @@ -44585,7 +44655,9 @@ patches.suse/pcmcia-ds-fix-refcount-leak-in-pcmcia_device_add.patch patches.suse/pcmcia-ds-fix-possible-name-leak-in-error-path-in-pc.patch patches.suse/regmap-prevent-noinc-writes-from-clobbering-cache.patch + patches.suse/drm-amd-pm-Fix-error-of-MACO-flag-setting-code.patch patches.suse/drm-amdgpu-don-t-use-ATRM-for-external-devices.patch + patches.suse/drm-amdgpu-smu13-drop-compute-workload-workaround.patch patches.suse/drm-amd-display-Avoid-NULL-dereference-of-timing-gen.patch patches.suse/s390-ap-fix-AP-bus-crash-on-early-config-change-callback-invocation.patch patches.suse/xfs-fix-units-conversion-error-in-xfs_bmap_del_extent_delay.patch @@ -44627,6 +44699,7 @@ patches.suse/drm-syncobj-fix-DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABL.patch patches.suse/drm-qxl-prevent-memory-leak.patch patches.suse/drm-amdgpu-fix-error-handling-in-amdgpu_bo_list_get.patch + patches.suse/drm-amdgpu-lower-CS-errors-to-debug-severity.patch patches.suse/drm-amdgpu-fix-software-pci_unplug-on-some-chips.patch patches.suse/fbdev-omapfb-Drop-unused-remove-function.patch patches.suse/fbdev-imsttfb-fix-double-free-in-probe.patch @@ -44643,7 +44716,10 @@ patches.suse/ALSA-hda-realtek-Enable-Mute-LED-on-HP-255-G10.patch patches.suse/ALSA-hda-realtek-Add-quirks-for-ASUS-2024-Zenbooks.patch patches.suse/ALSA-hda-realtek-Add-quirks-for-HP-Laptops.patch + patches.suse/drm-amd-display-Guard-against-invalid-RPTR-WPTR-bein.patch patches.suse/drm-amdgpu-correct-chunk_ptr-to-a-pointer-to-chunk.patch + patches.suse/drm-amd-display-fix-a-NULL-pointer-dereference-in-am.patch + patches.suse/drm-amd-display-Enable-fast-plane-updates-on-DCN3.2-.patch patches.suse/drm-amd-display-Change-the-DMCUB-mailbox-memory-loca.patch patches.suse/mm-kmem-drop-__GFP_NOFAIL-when-allocating-objcg-vectors.patch patches.suse/Revert-i2c-pxa-move-to-generic-GPIO-recovery.patch @@ -44670,6 +44746,7 @@ patches.suse/nvmet-nul-terminate-the-NQNs-passed-in-the-connect-c.patch patches.suse/nvme-move-nvme_stop_keep_alive-back-to-original-posi.patch patches.suse/ata-pata_isapnp-Add-missing-error-check-for-devm_iop.patch + patches.suse/drm-panel-auo-b101uan08.3-Fine-tune-the-panel-power-.patch patches.suse/drm-panel-simple-Fix-Innolux-G101ICE-L01-bus-flags.patch patches.suse/drm-panel-simple-Fix-Innolux-G101ICE-L01-timings.patch patches.suse/drm-rockchip-vop-Fix-color-for-RGB888-BGR888-format-.patch @@ -44711,8 +44788,17 @@ patches.suse/uapi-propagate-__struct_group-attributes-to-the-cont.patch patches.suse/dm-verity-initialize-fec-io-before-freeing-it-7be0.patch patches.suse/nvme-core-check-for-too-small-lba-shift.patch + patches.suse/drm-i915-Call-intel_pre_plane_updates-also-for-pipes.patch + patches.suse/drm-amd-display-Include-udelay-when-waiting-for-INBO.patch + patches.suse/drm-amdgpu-Force-order-between-a-read-and-write-to-t.patch + patches.suse/drm-amd-display-Use-DRAM-speed-from-validation-for-d.patch + patches.suse/drm-amd-display-Remove-min_dst_y_next_start-check-fo.patch + patches.suse/drm-amd-display-Update-min-Z8-residency-time-to-2100.patch patches.suse/drm-amdgpu-correct-the-amdgpu-runtime-dereference-us.patch + patches.suse/drm-amd-display-fix-ABM-disablement.patch patches.suse/drm-amd-display-update-dcn315-lpddr-pstate-latency.patch + patches.suse/drm-amd-pm-fix-a-memleak-in-aldebaran_tables_init.patch + patches.suse/drm-amd-Enable-PCIe-PME-from-D3.patch patches.suse/drm-amdgpu-Fix-cat-debugfs-amdgpu_regs_didt-causes-k.patch patches.suse/drm-amdgpu-Update-EEPROM-I2C-address-for-smu-v13_0_0.patch patches.suse/ALSA-hda-Fix-speaker-and-headset-mic-pin-config-for-.patch @@ -44753,6 +44839,7 @@ patches.suse/arm64-dts-rockchip-Expand-reg-size-of-vdec-node-for-RK3399.patch patches.suse/nouveau-tu102-flush-all-pdbs-on-vmm-flush.patch patches.suse/drm-bridge-tc358768-select-CONFIG_VIDEOMODE_HELPERS.patch + patches.suse/drm-amd-display-Increase-frame-warning-limit-with-KA.patch patches.suse/drm-amdgpu-Add-NULL-checks-for-function-pointers.patch patches.suse/drm-exynos-fix-a-potential-error-pointer-dereference.patch patches.suse/drm-exynos-fix-a-wrong-error-checking.patch @@ -44832,6 +44919,8 @@ patches.suse/drm-mediatek-Add-spinlock-for-setting-vblank-event-i.patch patches.suse/drm-i915-Fix-remapped-stride-with-CCS-on-ADL.patch patches.suse/drm-i915-Fix-intel_atomic_setup_scalers-plane_state-.patch + patches.suse/drm-amd-display-fix-hw-rotated-modes-when-PSR-SU-is-.patch + patches.suse/drm-amd-display-Disable-PSR-SU-on-Parade-0803-TCON-a.patch patches.suse/drm-amdgpu-sdma5.2-add-begin-end_use-ring-callbacks.patch patches.suse/drm-amdgpu-fix-tear-down-order-in-amdgpu_vm_pt_free.patch patches.suse/drm-crtc-Fix-uninit-value-bug-in-drm_mode_setcrtc.patch @@ -45135,6 +45224,7 @@ patches.suse/drm-radeon-check-the-alloc_workqueue-return-value-in.patch patches.suse/drm-radeon-dpm-fix-a-memleak-in-sumo_parse_power_tab.patch patches.suse/drm-radeon-trinity_dpm-fix-a-memleak-in-trinity_pars.patch + patches.suse/drm-amd-display-For-prefetch-mode-0-extend-prefetch-.patch patches.suse/drm-amdgpu-fix-ftrace-event-amdgpu_bo_move-always-mo.patch patches.suse/drm-amdgpu-debugfs-fix-error-code-when-smc-register-.patch patches.suse/drm-amd-pm-fix-a-double-free-in-si_dpm_init.patch @@ -45545,6 +45635,7 @@ patches.suse/ALSA-hda-realtek-fix-mute-micmute-LED-For-HP-mt440.patch patches.suse/efi-capsule-loader-fix-incorrect-allocation-size.patch patches.suse/mmc-core-Fix-eMMC-initialization-with-1-bit-bus-conn.patch + patches.suse/mmc-mmci-stm32-fix-DMA-API-overlapping-mappings-warn.patch patches.suse/mmc-sdhci-xenon-fix-PHY-init-clock-stability.patch patches.suse/mmc-sdhci-xenon-add-timeout-for-PHY-init-complete.patch patches.suse/btrfs-fix-double-free-of-anonymous-device-after-snap.patch @@ -45556,6 +45647,7 @@ patches.suse/dmaengine-fsl-qdma-fix-SoC-may-hang-on-16-byte-unali.patch patches.suse/dmaengine-fsl-qdma-init-irq-after-reg-initialization.patch patches.suse/dmaengine-ptdma-use-consistent-DMA-masks.patch + patches.suse/net-lan78xx-fix-runtime-PM-count-underflow-on-link-s.patch patches.suse/drm-i915-Check-before-removing-mm-notifier.patch patches.suse/drm-i915-selftests-Fix-dependency-of-some-timeouts-o.patch patches.suse/ALSA-hda-realtek-Fix-headset-Mic-no-show-at-resume-b.patch @@ -45698,14 +45790,36 @@ patches.suse/nilfs2-fix-failure-to-detect-DAT-corruption-in-btree.patch patches.suse/nilfs2-prevent-kernel-bug-at-submit_bh_wbc.patch patches.suse/media-staging-ipu3-imgu-Set-fields-before-media_enti.patch + patches.suse/media-xc4000-Fix-atomicity-violation-in-xc4000_get_f.patch + patches.suse/media-em28xx-annotate-unchecked-call-to-media_device.patch + patches.suse/media-v4l2-tpg-fix-some-memleaks-in-tpg_alloc.patch + patches.suse/media-v4l2-mem2mem-fix-a-memleak-in-v4l2_m2m_registe.patch + patches.suse/media-edia-dvbdev-fix-a-use-after-free.patch + patches.suse/media-sun8i-di-Fix-coefficient-writes.patch + patches.suse/media-sun8i-di-Fix-power-on-off-sequences.patch + patches.suse/media-sun8i-di-Fix-chroma-difference-threshold.patch patches.suse/media-imx-csc-scaler-fix-v4l2_ctrl_handler-memory-le.patch + patches.suse/media-go7007-add-check-of-return-value-of-go7007_rea.patch + patches.suse/media-pvrusb2-remove-redundant-NULL-check.patch + patches.suse/media-pvrusb2-fix-pvr2_stream_callback-casts.patch + patches.suse/media-pvrusb2-fix-uaf-in-pvr2_context_set_notify.patch + patches.suse/media-dvb-frontends-avoid-stack-overflow-warnings-wi.patch + patches.suse/media-go7007-fix-a-memleak-in-go7007_load_encoder.patch + patches.suse/media-ttpci-fix-two-memleaks-in-budget_av_attach.patch + patches.suse/media-usbtv-Remove-useless-locks-in-usbtv_video_free.patch patches.suse/clk-zynq-Prevent-null-pointer-dereference-caused-by-.patch + patches.suse/mtd-maps-physmap-core-fix-flash-size-larger-than-32-.patch + patches.suse/mtd-rawnand-meson-fix-scrambling-mode-value-in-comma.patch + patches.suse/mtd-rawnand-lpc32xx_mlc-fix-irq-handler-prototype.patch patches.suse/KVM-s390-only-deliver-the-set-service-event-bits.patch + patches.suse/crypto-xilinx-call-finalize-with-bh-disabled.patch + patches.suse/crypto-arm-sha-fix-function-cast-warnings.patch patches.suse/powerpc-pseries-Fix-potential-memleak-in-papr_get_at.patch patches.suse/net-sunrpc-Fix-an-off-by-one-in-rpc_sockaddr2uaddr.patch patches.suse/NFSv4.2-fix-nfs4_listxattr-kernel-BUG-at-mm-usercopy.patch patches.suse/NFSv4.2-fix-listxattr-maximum-XDR-buffer-size.patch patches.suse/NFS-Fix-an-off-by-one-in-root_nfs_cat.patch + patches.suse/watchdog-stm32_iwdg-initialize-default-timeout.patch patches.suse/RDMA-irdma-Remove-duplicate-assignment.patch patches.suse/RDMA-srpt-Do-not-register-event-handler-until-srpt-d.patch patches.suse/RDMA-hns-Fix-mis-modifying-default-congestion-contro.patch