diff --git a/patches.suse/PCI-aardvark-Fix-checking-for-PIO-status.patch b/patches.suse/PCI-aardvark-Fix-checking-for-PIO-status.patch new file mode 100644 index 0000000..a727028 --- /dev/null +++ b/patches.suse/PCI-aardvark-Fix-checking-for-PIO-status.patch @@ -0,0 +1,160 @@ +From: Evan Wang +Date: Thu, 22 Jul 2021 16:40:38 +0200 +Subject: PCI: aardvark: Fix checking for PIO status +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit +Git-commit: fcb461e2bc8b83b7eaca20cb2221e8b940f2189c +Patch-mainline: 5.15-rc1 +References: git-fixes + +There is an issue that when PCIe switch is connected to an Armada 3700 +board, there will be lots of warnings about PIO errors when reading the +config space. According to Aardvark PIO read and write sequence in HW +specification, the current way to check PIO status has the following +issues: + +1) For PIO read operation, it reports the error message, which should be + avoided according to HW specification. + +2) For PIO read and write operations, it only checks PIO operation complete + status, which is not enough, and error status should also be checked. + +This patch aligns the code with Aardvark PIO read and write sequence in HW +specification on PIO status check and fix the warnings when reading config +space. + +[pali: Fix CRS handling when CRSSVE is not enabled] + +Link: https://lore.kernel.org/r/20210722144041.12661-2-pali@kernel.org +Tested-by: Victor Gu +Signed-off-by: Evan Wang +Signed-off-by: Pali Rohár +Signed-off-by: Lorenzo Pieralisi +Reviewed-by: Victor Gu +Reviewed-by: Marek Behún +Cc: stable@vger.kernel.org # b1bd5714472c ("PCI: aardvark: Indicate error in 'val' when config read fails") +Signed-off-by: Jiri Slaby +--- + drivers/pci/host/pci-aardvark.c | 62 ++++++++++++++++++++++++++++++++++------ + 1 file changed, 54 insertions(+), 8 deletions(-) + +--- a/drivers/pci/host/pci-aardvark.c ++++ b/drivers/pci/host/pci-aardvark.c +@@ -57,6 +57,7 @@ + #define PIO_COMPLETION_STATUS_CRS 2 + #define PIO_COMPLETION_STATUS_CA 4 + #define PIO_NON_POSTED_REQ BIT(10) ++#define PIO_ERR_STATUS BIT(11) + #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8) + #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc) + #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10) +@@ -399,7 +400,7 @@ static void advk_pcie_setup_hw(struct ad + advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); + } + +-static void advk_pcie_check_pio_status(struct advk_pcie *pcie) ++static int advk_pcie_check_pio_status(struct advk_pcie *pcie, u32 *val) + { + struct device *dev = &pcie->pdev->dev; + u32 reg; +@@ -410,14 +411,49 @@ static void advk_pcie_check_pio_status(s + status = (reg & PIO_COMPLETION_STATUS_MASK) >> + PIO_COMPLETION_STATUS_SHIFT; + +- if (!status) +- return; +- ++ /* ++ * According to HW spec, the PIO status check sequence as below: ++ * 1) even if COMPLETION_STATUS(bit9:7) indicates successful, ++ * it still needs to check Error Status(bit11), only when this bit ++ * indicates no error happen, the operation is successful. ++ * 2) value Unsupported Request(1) of COMPLETION_STATUS(bit9:7) only ++ * means a PIO write error, and for PIO read it is successful with ++ * a read value of 0xFFFFFFFF. ++ * 3) value Completion Retry Status(CRS) of COMPLETION_STATUS(bit9:7) ++ * only means a PIO write error, and for PIO read it is successful ++ * with a read value of 0xFFFF0001. ++ * 4) value Completer Abort (CA) of COMPLETION_STATUS(bit9:7) means ++ * error for both PIO read and PIO write operation. ++ * 5) other errors are indicated as 'unknown'. ++ */ + switch (status) { ++ case PIO_COMPLETION_STATUS_OK: ++ if (reg & PIO_ERR_STATUS) { ++ strcomp_status = "COMP_ERR"; ++ break; ++ } ++ /* Get the read result */ ++ if (val) ++ *val = advk_readl(pcie, PIO_RD_DATA); ++ /* No error */ ++ strcomp_status = NULL; ++ break; + case PIO_COMPLETION_STATUS_UR: + strcomp_status = "UR"; + break; + case PIO_COMPLETION_STATUS_CRS: ++ /* PCIe r4.0, sec 2.3.2, says: ++ * If CRS Software Visibility is not enabled, the Root Complex ++ * must re-issue the Configuration Request as a new Request. ++ * A Root Complex implementation may choose to limit the number ++ * of Configuration Request/CRS Completion Status loops before ++ * determining that something is wrong with the target of the ++ * Request and taking appropriate action, e.g., complete the ++ * Request to the host as a failed transaction. ++ * ++ * To simplify implementation do not re-issue the Configuration ++ * Request and complete the Request as a failed transaction. ++ */ + strcomp_status = "CRS"; + break; + case PIO_COMPLETION_STATUS_CA: +@@ -428,6 +464,9 @@ static void advk_pcie_check_pio_status(s + break; + } + ++ if (!strcomp_status) ++ return 0; ++ + if (reg & PIO_NON_POSTED_REQ) + str_posted = "Non-posted"; + else +@@ -435,6 +474,8 @@ static void advk_pcie_check_pio_status(s + + dev_err(dev, "%s PIO Response Status: %s, %#x @ %#x\n", + str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS)); ++ ++ return -EFAULT; + } + + static int advk_pcie_wait_pio(struct advk_pcie *pcie) +@@ -545,10 +586,13 @@ static int advk_pcie_rd_conf(struct pci_ + return PCIBIOS_SET_FAILED; + } + +- advk_pcie_check_pio_status(pcie); ++ /* Check PIO status and get the read result */ ++ ret = advk_pcie_check_pio_status(pcie, val); ++ if (ret < 0) { ++ *val = 0xffffffff; ++ return PCIBIOS_SET_FAILED; ++ } + +- /* Get the read result */ +- *val = advk_readl(pcie, PIO_RD_DATA); + if (size == 1) + *val = (*val >> (8 * (where & 3))) & 0xff; + else if (size == 2) +@@ -608,7 +652,9 @@ static int advk_pcie_wr_conf(struct pci_ + if (ret < 0) + return PCIBIOS_SET_FAILED; + +- advk_pcie_check_pio_status(pcie); ++ ret = advk_pcie_check_pio_status(pcie, NULL); ++ if (ret < 0) ++ return PCIBIOS_SET_FAILED; + + return PCIBIOS_SUCCESSFUL; + } diff --git a/series.conf b/series.conf index 89fd358..176fa50 100644 --- a/series.conf +++ b/series.conf @@ -61601,6 +61601,7 @@ patches.suse/PCI-Restrict-ASMedia-ASM1062-SATA-Max-Payload-Size-S.patch patches.suse/PCI-Return-0-data-on-pciconfig_read-CAP_SYS_ADMIN-fa.patch patches.suse/PCI-Add-ACS-quirks-for-Cavium-multi-function-devices.patch + patches.suse/PCI-aardvark-Fix-checking-for-PIO-status.patch patches.suse/msft-hv-2426-PCI-hv-Support-for-create-interrupt-v3.patch patches.suse/profiling-fix-shift-out-of-bounds-bugs.patch patches.suse/prctl-allow-to-setup-brk-for-et_dyn-executables.patch