From: Andres Rodriguez Date: Fri, 3 Feb 2017 16:17:15 -0500 Subject: drm/radeon: take ownership of pipe initialization MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Git-commit: d59095f7dd8810e67bdad7a65131903646ebc444 Patch-mainline: v4.13-rc1 References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166 Take ownership of pipe initialization away from KFD. Note that hpd_eop_gpu_addr was already large enough to accomodate all pipes. Reviewed-by: Edward O'Callaghan Reviewed-by: Felix Kuehling Acked-by: Christian König Signed-off-by: Andres Rodriguez Signed-off-by: Alex Deucher Acked-by: Petr Tesarik --- drivers/gpu/drm/radeon/cik.c | 31 ++++++++++++++++--------------- drivers/gpu/drm/radeon/radeon_kfd.c | 13 +------------ 2 files changed, 17 insertions(+), 27 deletions(-) --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -4580,23 +4580,24 @@ static int cik_cp_compute_resume(struct /* init the pipes */ mutex_lock(&rdev->srbm_mutex); - eop_gpu_addr = rdev->mec.hpd_eop_gpu_addr; + for (i = 0; i < rdev->mec.num_pipe; ++i) { + cik_srbm_select(rdev, 0, i, 0, 0); - cik_srbm_select(rdev, 0, 0, 0, 0); - - /* write the EOP addr */ - WREG32(CP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8); - WREG32(CP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8); - - /* set the VMID assigned */ - WREG32(CP_HPD_EOP_VMID, 0); - - /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ - tmp = RREG32(CP_HPD_EOP_CONTROL); - tmp &= ~EOP_SIZE_MASK; - tmp |= order_base_2(MEC_HPD_SIZE / 8); - WREG32(CP_HPD_EOP_CONTROL, tmp); + eop_gpu_addr = rdev->mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2) ; + /* write the EOP addr */ + WREG32(CP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8); + WREG32(CP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8); + + /* set the VMID assigned */ + WREG32(CP_HPD_EOP_VMID, 0); + + /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ + tmp = RREG32(CP_HPD_EOP_CONTROL); + tmp &= ~EOP_SIZE_MASK; + tmp |= order_base_2(MEC_HPD_SIZE / 8); + WREG32(CP_HPD_EOP_CONTROL, tmp); + } mutex_unlock(&rdev->srbm_mutex); /* init the queues. Just two for now. */ --- a/drivers/gpu/drm/radeon/radeon_kfd.c +++ b/drivers/gpu/drm/radeon/radeon_kfd.c @@ -423,18 +423,7 @@ static int kgd_set_pasid_vmid_mapping(st static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id, uint32_t hpd_size, uint64_t hpd_gpu_addr) { - uint32_t mec = (pipe_id / CIK_PIPE_PER_MEC) + 1; - uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC); - - lock_srbm(kgd, mec, pipe, 0, 0); - write_register(kgd, CP_HPD_EOP_BASE_ADDR, - lower_32_bits(hpd_gpu_addr >> 8)); - write_register(kgd, CP_HPD_EOP_BASE_ADDR_HI, - upper_32_bits(hpd_gpu_addr >> 8)); - write_register(kgd, CP_HPD_EOP_VMID, 0); - write_register(kgd, CP_HPD_EOP_CONTROL, hpd_size); - unlock_srbm(kgd); - + /* nothing to do here */ return 0; }