diff --git a/patches.suse/spi-spi-imx-fix-MX51_ECSPI_-macros-when-cs-3.patch b/patches.suse/spi-spi-imx-fix-MX51_ECSPI_-macros-when-cs-3.patch
new file mode 100644
index 0000000..03d09cc
--- /dev/null
+++ b/patches.suse/spi-spi-imx-fix-MX51_ECSPI_-macros-when-cs-3.patch
@@ -0,0 +1,80 @@
+From 87c614175bbf28d3fd076dc2d166bac759e41427 Mon Sep 17 00:00:00 2001
+From: Kevin Groeneveld <kgroeneveld@lenbrook.com>
+Date: Sat, 18 Mar 2023 18:21:32 -0400
+Subject: [PATCH] spi: spi-imx: fix MX51_ECSPI_* macros when cs > 3
+Mime-version: 1.0
+Content-type: text/plain; charset=UTF-8
+Content-transfer-encoding: 8bit
+Git-commit: 87c614175bbf28d3fd076dc2d166bac759e41427
+Patch-mainline: v6.4-rc1
+References: git-fixes
+
+When using gpio based chip select the cs value can go outside the range
+0 – 3. The various MX51_ECSPI_* macros did not take this into consideration
+resulting in possible corruption of the configuration.
+
+For example for any cs value over 3 the SCLKPHA bits would not be set and
+other values in the register possibly corrupted.
+
+One way to fix this is to just mask the cs bits to 2 bits. This still
+allows all 4 native chip selects to work as well as gpio chip selects
+(which can use any of the 4 chip select configurations).
+
+Signed-off-by: Kevin Groeneveld <kgroeneveld@lenbrook.com>
+Link: https://lore.kernel.org/r/20230318222132.3373-1-kgroeneveld@lenbrook.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Acked-by: Takashi Iwai <tiwai@suse.de>
+
+---
+ drivers/spi/spi-imx.c | 24 ++++++++++++++++++------
+ 1 file changed, 18 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
+index 1f2c7ad65ec8..24390c702c60 100644
+--- a/drivers/spi/spi-imx.c
++++ b/drivers/spi/spi-imx.c
+@@ -252,6 +252,18 @@ static bool spi_imx_can_dma(struct spi_controller *controller, struct spi_device
+ 	return true;
+ }
+ 
++/*
++ * Note the number of natively supported chip selects for MX51 is 4. Some
++ * devices may have less actual SS pins but the register map supports 4. When
++ * using gpio chip selects the cs values passed into the macros below can go
++ * outside the range 0 - 3. We therefore need to limit the cs value to avoid
++ * corrupting bits outside the allocated locations.
++ *
++ * The simplest way to do this is to just mask the cs bits to 2 bits. This
++ * still allows all 4 native chip selects to work as well as gpio chip selects
++ * (which can use any of the 4 chip select configurations).
++ */
++
+ #define MX51_ECSPI_CTRL		0x08
+ #define MX51_ECSPI_CTRL_ENABLE		(1 <<  0)
+ #define MX51_ECSPI_CTRL_XCH		(1 <<  2)
+@@ -260,16 +272,16 @@ static bool spi_imx_can_dma(struct spi_controller *controller, struct spi_device
+ #define MX51_ECSPI_CTRL_DRCTL(drctl)	((drctl) << 16)
+ #define MX51_ECSPI_CTRL_POSTDIV_OFFSET	8
+ #define MX51_ECSPI_CTRL_PREDIV_OFFSET	12
+-#define MX51_ECSPI_CTRL_CS(cs)		((cs) << 18)
++#define MX51_ECSPI_CTRL_CS(cs)		((cs & 3) << 18)
+ #define MX51_ECSPI_CTRL_BL_OFFSET	20
+ #define MX51_ECSPI_CTRL_BL_MASK		(0xfff << 20)
+ 
+ #define MX51_ECSPI_CONFIG	0x0c
+-#define MX51_ECSPI_CONFIG_SCLKPHA(cs)	(1 << ((cs) +  0))
+-#define MX51_ECSPI_CONFIG_SCLKPOL(cs)	(1 << ((cs) +  4))
+-#define MX51_ECSPI_CONFIG_SBBCTRL(cs)	(1 << ((cs) +  8))
+-#define MX51_ECSPI_CONFIG_SSBPOL(cs)	(1 << ((cs) + 12))
+-#define MX51_ECSPI_CONFIG_SCLKCTL(cs)	(1 << ((cs) + 20))
++#define MX51_ECSPI_CONFIG_SCLKPHA(cs)	(1 << ((cs & 3) +  0))
++#define MX51_ECSPI_CONFIG_SCLKPOL(cs)	(1 << ((cs & 3) +  4))
++#define MX51_ECSPI_CONFIG_SBBCTRL(cs)	(1 << ((cs & 3) +  8))
++#define MX51_ECSPI_CONFIG_SSBPOL(cs)	(1 << ((cs & 3) + 12))
++#define MX51_ECSPI_CONFIG_SCLKCTL(cs)	(1 << ((cs & 3) + 20))
+ 
+ #define MX51_ECSPI_INT		0x10
+ #define MX51_ECSPI_INT_TEEN		(1 <<  0)
+-- 
+2.35.3
+
diff --git a/series.conf b/series.conf
index cfb8ecf..ba170aa 100644
--- a/series.conf
+++ b/series.conf
@@ -19965,6 +19965,7 @@
 	patches.suse/ASoC-cs35l41-Only-disable-internal-boost.patch
 	patches.suse/ASoC-es8316-Handle-optional-IRQ-assignment.patch
 	patches.suse/ASoC-fsl_mqs-move-of_node_put-to-the-correct-locatio.patch
+	patches.suse/spi-spi-imx-fix-MX51_ECSPI_-macros-when-cs-3.patch
 	patches.suse/spi-qup-Don-t-skip-cleanup-in-remove-s-error-path.patch
 	patches.suse/spi-fsl-spi-Fix-CPM-QE-mode-Litte-Endian.patch
 	patches.suse/spi-cadence-quadspi-fix-suspend-resume-implementatio.patch