diff --git a/blacklist.conf b/blacklist.conf index 77fcdce..30f2120 100644 --- a/blacklist.conf +++ b/blacklist.conf @@ -2798,3 +2798,8 @@ b648ab487f31bc4c38941bc770ea97fe394304bb # we don't have the original commit, no a1ae8d4d9be0178132df7c4931a1ba77d0e76039 # no nvme core/fabric fixes to missing infrastructure 2a587b9ad052e7e92e508aea90c1e2ae433c1908 # ARCH_ASPEED=n 5d3d01ae15d2f37ed0325c99ab47ef0ae5d05f3c # a change of a name must break kABI +ea401499e943c307e6d44af6c2b4e068643e7884 # unavoidable kABI brekage of struct pcie_port_service_driver +f192970de860d3ab90aa9e2a22853201a57bde78 # not needed +4966babd904d7f8e9e20735f3637a98fd7ca538c # CONFIG_ROSE is not set +de526f401284e1638d4c97cb5a4c292ac3f37655 # not needed +0e5a82efda872c2469c210957d7d4161ef8f4391 # not needed diff --git a/patches.suse/PCI-Add-ACS-quirks-for-Cavium-multi-function-devices.patch b/patches.suse/PCI-Add-ACS-quirks-for-Cavium-multi-function-devices.patch new file mode 100644 index 0000000..3bbb34b --- /dev/null +++ b/patches.suse/PCI-Add-ACS-quirks-for-Cavium-multi-function-devices.patch @@ -0,0 +1,37 @@ +From: George Cherian +Date: Tue, 10 Aug 2021 17:54:25 +0530 +Subject: PCI: Add ACS quirks for Cavium multi-function devices +Git-commit: 32837d8a8f63eb95dcb9cd005524a27f06478832 +Patch-mainline: 5.15-rc1 +References: git-fixes + +Some Cavium endpoints are implemented as multi-function devices without ACS +capability, but they actually don't support peer-to-peer transactions. + +Add ACS quirks to declare DMA isolation for the following devices: + + - BGX device found on Octeon-TX (8xxx) + - CGX device found on Octeon-TX2 (9xxx) + - RPM device found on Octeon-TX3 (10xxx) + +Link: https://lore.kernel.org/r/20210810122425.1115156-1-george.cherian@marvell.com +Signed-off-by: George Cherian +Signed-off-by: Bjorn Helgaas +Signed-off-by: Jiri Slaby +--- + drivers/pci/quirks.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/pci/quirks.c ++++ b/drivers/pci/quirks.c +@@ -4910,6 +4910,10 @@ static const struct pci_dev_acs_enabled + { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */ + /* Cavium ThunderX */ + { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs }, ++ /* Cavium multi-function devices */ ++ { PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs }, ++ { PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs }, ++ { PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs }, + /* APM X-Gene */ + { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs }, + /* Ampere Computing */ diff --git a/patches.suse/PCI-Call-Max-Payload-Size-related-fixup-quirks-early.patch b/patches.suse/PCI-Call-Max-Payload-Size-related-fixup-quirks-early.patch new file mode 100644 index 0000000..b5e5965 --- /dev/null +++ b/patches.suse/PCI-Call-Max-Payload-Size-related-fixup-quirks-early.patch @@ -0,0 +1,47 @@ +From: =?UTF-8?q?Marek=20Beh=C3=BAn?= +Date: Thu, 24 Jun 2021 19:14:17 +0200 +Subject: PCI: Call Max Payload Size-related fixup quirks early +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit +Git-commit: b8da302e2955fe4d41eb9d48199242674d77dbe0 +Patch-mainline: 5.15-rc1 +References: git-fixes + +pci_device_add() calls HEADER fixups after pci_configure_device(), which +configures Max Payload Size. + +Convert MPS-related fixups to EARLY fixups so pci_configure_mps() takes +them into account. + +Fixes: 27d868b5e6cfa ("PCI: Set MPS to match upstream bridge") +Link: https://lore.kernel.org/r/20210624171418.27194-1-kabel@kernel.org +Signed-off-by: Marek Behún +Signed-off-by: Bjorn Helgaas +Cc: stable@vger.kernel.org +Signed-off-by: Jiri Slaby +--- + drivers/pci/quirks.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +--- a/drivers/pci/quirks.c ++++ b/drivers/pci/quirks.c +@@ -3061,12 +3061,12 @@ static void fixup_mpss_256(struct pci_de + { + dev->pcie_mpss = 1; /* 256 bytes */ + } +-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, +- PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); +-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, +- PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); +-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, +- PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, ++ PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, ++ PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, ++ PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); + + /* Intel 5000 and 5100 Memory controllers have an errata with read completion + * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. diff --git a/patches.suse/PCI-Mark-Atheros-QCA6174-to-avoid-bus-reset.patch b/patches.suse/PCI-Mark-Atheros-QCA6174-to-avoid-bus-reset.patch new file mode 100644 index 0000000..61c2ded --- /dev/null +++ b/patches.suse/PCI-Mark-Atheros-QCA6174-to-avoid-bus-reset.patch @@ -0,0 +1,36 @@ +From: Ingmar Klein +Date: Fri, 9 Apr 2021 11:26:33 +0200 +Subject: PCI: Mark Atheros QCA6174 to avoid bus reset +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit +Git-commit: e3f4bd3462f6f796594ecc0dda7144ed2d1e5a26 +Patch-mainline: 5.16-rc1 +References: git-fixes + +When passing the Atheros QCA6174 through to a virtual machine, the VM hangs +at the point where the ath10k driver loads. + +Add a quirk to avoid bus resets on this device, which avoids the hang. + +[bhelgaas: commit log] +Link: https://lore.kernel.org/r/08982e05-b6e8-5a8d-24ab-da1488ee50a8@web.de +Signed-off-by: Ingmar Klein +Signed-off-by: Bjorn Helgaas +Reviewed-by: Pali Rohár +Cc: stable@vger.kernel.org +Signed-off-by: Jiri Slaby +--- + drivers/pci/quirks.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/pci/quirks.c ++++ b/drivers/pci/quirks.c +@@ -3443,6 +3443,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_A + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset); + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset); + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset); + + /* + * Root port on some Cavium CN8xxx chips do not successfully complete a bus diff --git a/patches.suse/PCI-Restrict-ASMedia-ASM1062-SATA-Max-Payload-Size-S.patch b/patches.suse/PCI-Restrict-ASMedia-ASM1062-SATA-Max-Payload-Size-S.patch new file mode 100644 index 0000000..4d61112 --- /dev/null +++ b/patches.suse/PCI-Restrict-ASMedia-ASM1062-SATA-Max-Payload-Size-S.patch @@ -0,0 +1,50 @@ +From: =?UTF-8?q?Marek=20Beh=C3=BAn?= +Date: Thu, 24 Jun 2021 19:14:18 +0200 +Subject: PCI: Restrict ASMedia ASM1062 SATA Max Payload Size Supported +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit +Git-commit: b12d93e9958e028856cbcb061b6e64728ca07755 +Patch-mainline: 5.15-rc1 +References: git-fixes + +The ASMedia ASM1062 SATA controller advertises Max_Payload_Size_Supported +of 512, but in fact it cannot handle incoming TLPs with payload size of +512. + +We discovered this issue on PCIe controllers capable of MPS = 512 (Aardvark +and DesignWare), where the issue presents itself as an External Abort. +Bjorn Helgaas says: + + Probably ASM1062 reports a Malformed TLP error when it receives a data + payload of 512 bytes, and Aardvark, DesignWare, etc convert this to an + arm64 External Abort. [1] + +To avoid this problem, limit the ASM1062 Max Payload Size Supported to 256 +bytes, so we set the Max Payload Size of devices that may send TLPs to the +ASM1062 to 256 or less. + +[1] https://lore.kernel.org/linux-pci/20210601170907.GA1949035@bjorn-Precision-5520/ +BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=212695 +Link: https://lore.kernel.org/r/20210624171418.27194-2-kabel@kernel.org +Reported-by: Rötti +Signed-off-by: Marek Behún +Signed-off-by: Bjorn Helgaas +Reviewed-by: Krzysztof Wilczyński +Reviewed-by: Pali Rohár +Cc: stable@vger.kernel.org +Signed-off-by: Jiri Slaby +--- + drivers/pci/quirks.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/pci/quirks.c ++++ b/drivers/pci/quirks.c +@@ -3067,6 +3067,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SO + PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); + DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, + PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256); + + /* Intel 5000 and 5100 Memory controllers have an errata with read completion + * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. diff --git a/patches.suse/PCI-Return-0-data-on-pciconfig_read-CAP_SYS_ADMIN-fa.patch b/patches.suse/PCI-Return-0-data-on-pciconfig_read-CAP_SYS_ADMIN-fa.patch new file mode 100644 index 0000000..2a6b811 --- /dev/null +++ b/patches.suse/PCI-Return-0-data-on-pciconfig_read-CAP_SYS_ADMIN-fa.patch @@ -0,0 +1,54 @@ +From: =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= +Date: Thu, 29 Jul 2021 23:37:54 +0000 +Subject: PCI: Return ~0 data on pciconfig_read() CAP_SYS_ADMIN failure +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit +Git-commit: a8bd29bd49c4156ea0ec5a97812333e2aeef44e7 +Patch-mainline: 5.15-rc1 +References: git-fixes + +The pciconfig_read() syscall reads PCI configuration space using +hardware-dependent config accessors. + +If the read fails on PCI, most accessors don't return an error; they +pretend the read was successful and got ~0 data from the device, so the +syscall returns success with ~0 data in the buffer. + +When the accessor does return an error, pciconfig_read() normally fills the +user's buffer with ~0 and returns an error in errno. But after +e4585da22ad0 ("pci syscall.c: Switch to refcounting API"), we don't fill +the buffer with ~0 for the EPERM "user lacks CAP_SYS_ADMIN" error. + +Userspace may rely on the ~0 data to detect errors, but after e4585da22ad0, +that would not detect CAP_SYS_ADMIN errors. + +Restore the original behaviour of filling the buffer with ~0 when the +CAP_SYS_ADMIN check fails. + +[bhelgaas: commit log, fold in Nathan's fix +https://lore.kernel.org/r/20210803200836.500658-1-nathan@kernel.org] +Fixes: e4585da22ad0 ("pci syscall.c: Switch to refcounting API") +Link: https://lore.kernel.org/r/20210729233755.1509616-1-kw@linux.com +Signed-off-by: Krzysztof Wilczyński +Signed-off-by: Bjorn Helgaas +Cc: stable@vger.kernel.org +Signed-off-by: Jiri Slaby +--- + drivers/pci/syscall.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/drivers/pci/syscall.c ++++ b/drivers/pci/syscall.c +@@ -23,8 +23,10 @@ SYSCALL_DEFINE5(pciconfig_read, unsigned + long err; + int cfg_ret; + ++ err = -EPERM; ++ dev = NULL; + if (!capable(CAP_SYS_ADMIN)) +- return -EPERM; ++ goto error; + + err = -ENODEV; + dev = pci_get_bus_and_slot(bus, dfn); diff --git a/patches.suse/PCI-aardvark-Configure-PCIe-resources-from-ranges-DT.patch b/patches.suse/PCI-aardvark-Configure-PCIe-resources-from-ranges-DT.patch new file mode 100644 index 0000000..b8358c9 --- /dev/null +++ b/patches.suse/PCI-aardvark-Configure-PCIe-resources-from-ranges-DT.patch @@ -0,0 +1,297 @@ +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= +Date: Thu, 24 Jun 2021 23:55:45 +0200 +Subject: PCI: aardvark: Configure PCIe resources from 'ranges' DT property +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit +Git-commit: 64f160e19e9264a7f6d89c516baae1473b6f8359 +Patch-mainline: 5.15-rc1 +References: git-fixes + +In commit 6df6ba974a55 ("PCI: aardvark: Remove PCIe outbound window +configuration") was removed aardvark PCIe outbound window configuration and +commit description said that was recommended solution by HW designers. + +But that commit completely removed support for configuring PCIe IO +resources without removing PCIe IO 'ranges' from DTS files. After that +commit PCIe IO space started to be treated as PCIe MEM space and accessing +it just caused kernel crash. + +Moreover implementation of PCIe outbound windows prior that commit was +incorrect. It completely ignored offset between CPU address and PCIe bus +address and expected that in DTS is CPU address always same as PCIe bus +address without doing any checks. Also it completely ignored size of every +PCIe resource specified in 'ranges' DTS property and expected that every +PCIe resource has size 128 MB (also for PCIe IO range). Again without any +check. Apparently none of PCIe resource has in DTS specified size of 128 +MB. So it was completely broken and thanks to how aardvark mask works, +configuration was completely ignored. + +This patch reverts back support for PCIe outbound window configuration but +implementation is a new without issues mentioned above. PCIe outbound +window is required when DTS specify in 'ranges' property non-zero offset +between CPU and PCIe address space. To address recommendation by HW +designers as specified in commit description of 6df6ba974a55, set default +outbound parameters as PCIe MEM access without translation and therefore +for this PCIe 'ranges' it is not needed to configure PCIe outbound window. +For PCIe IO space is needed to configure aardvark PCIe outbound window. + +This patch fixes kernel crash when trying to access PCIe IO space. + +[js] no .remove + +Link: https://lore.kernel.org/r/20210624215546.4015-2-pali@kernel.org +Signed-off-by: Pali Rohár +Signed-off-by: Lorenzo Pieralisi +Cc: stable@vger.kernel.org # 6df6ba974a55 ("PCI: aardvark: Remove PCIe outbound window configuration") +Signed-off-by: Jiri Slaby +--- + drivers/pci/host/pci-aardvark.c | 190 +++++++++++++++++++++++++++++++++++++++- + 1 file changed, 189 insertions(+), 1 deletion(-) + +--- a/drivers/pci/host/pci-aardvark.c ++++ b/drivers/pci/host/pci-aardvark.c +@@ -114,6 +114,46 @@ + #define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C) + #define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C) + ++/* PCIe window configuration */ ++#define OB_WIN_BASE_ADDR 0x4c00 ++#define OB_WIN_BLOCK_SIZE 0x20 ++#define OB_WIN_COUNT 8 ++#define OB_WIN_REG_ADDR(win, offset) (OB_WIN_BASE_ADDR + \ ++ OB_WIN_BLOCK_SIZE * (win) + \ ++ (offset)) ++#define OB_WIN_MATCH_LS(win) OB_WIN_REG_ADDR(win, 0x00) ++#define OB_WIN_ENABLE BIT(0) ++#define OB_WIN_MATCH_MS(win) OB_WIN_REG_ADDR(win, 0x04) ++#define OB_WIN_REMAP_LS(win) OB_WIN_REG_ADDR(win, 0x08) ++#define OB_WIN_REMAP_MS(win) OB_WIN_REG_ADDR(win, 0x0c) ++#define OB_WIN_MASK_LS(win) OB_WIN_REG_ADDR(win, 0x10) ++#define OB_WIN_MASK_MS(win) OB_WIN_REG_ADDR(win, 0x14) ++#define OB_WIN_ACTIONS(win) OB_WIN_REG_ADDR(win, 0x18) ++#define OB_WIN_DEFAULT_ACTIONS (OB_WIN_ACTIONS(OB_WIN_COUNT-1) + 0x4) ++#define OB_WIN_FUNC_NUM_MASK GENMASK(31, 24) ++#define OB_WIN_FUNC_NUM_SHIFT 24 ++#define OB_WIN_FUNC_NUM_ENABLE BIT(23) ++#define OB_WIN_BUS_NUM_BITS_MASK GENMASK(22, 20) ++#define OB_WIN_BUS_NUM_BITS_SHIFT 20 ++#define OB_WIN_MSG_CODE_ENABLE BIT(22) ++#define OB_WIN_MSG_CODE_MASK GENMASK(21, 14) ++#define OB_WIN_MSG_CODE_SHIFT 14 ++#define OB_WIN_MSG_PAYLOAD_LEN BIT(12) ++#define OB_WIN_ATTR_ENABLE BIT(11) ++#define OB_WIN_ATTR_TC_MASK GENMASK(10, 8) ++#define OB_WIN_ATTR_TC_SHIFT 8 ++#define OB_WIN_ATTR_RELAXED BIT(7) ++#define OB_WIN_ATTR_NOSNOOP BIT(6) ++#define OB_WIN_ATTR_POISON BIT(5) ++#define OB_WIN_ATTR_IDO BIT(4) ++#define OB_WIN_TYPE_MASK GENMASK(3, 0) ++#define OB_WIN_TYPE_SHIFT 0 ++#define OB_WIN_TYPE_MEM 0x0 ++#define OB_WIN_TYPE_IO 0x4 ++#define OB_WIN_TYPE_CONFIG_TYPE0 0x8 ++#define OB_WIN_TYPE_CONFIG_TYPE1 0x9 ++#define OB_WIN_TYPE_MSG 0xc ++ + /* LMI registers base address and register offsets */ + #define LMI_BASE_ADDR 0x6000 + #define CFG_REG (LMI_BASE_ADDR + 0x0) +@@ -182,6 +222,13 @@ struct advk_pcie { + struct platform_device *pdev; + void __iomem *base; + struct list_head resources; ++ struct { ++ phys_addr_t match; ++ phys_addr_t remap; ++ phys_addr_t mask; ++ u32 actions; ++ } wins[OB_WIN_COUNT]; ++ u8 wins_count; + struct irq_domain *irq_domain; + struct irq_chip irq_chip; + struct irq_domain *msi_domain; +@@ -309,9 +356,39 @@ err: + dev_err(dev, "link never came up\n"); + } + ++/* ++ * Set PCIe address window register which could be used for memory ++ * mapping. ++ */ ++static void advk_pcie_set_ob_win(struct advk_pcie *pcie, u8 win_num, ++ phys_addr_t match, phys_addr_t remap, ++ phys_addr_t mask, u32 actions) ++{ ++ advk_writel(pcie, OB_WIN_ENABLE | ++ lower_32_bits(match), OB_WIN_MATCH_LS(win_num)); ++ advk_writel(pcie, upper_32_bits(match), OB_WIN_MATCH_MS(win_num)); ++ advk_writel(pcie, lower_32_bits(remap), OB_WIN_REMAP_LS(win_num)); ++ advk_writel(pcie, upper_32_bits(remap), OB_WIN_REMAP_MS(win_num)); ++ advk_writel(pcie, lower_32_bits(mask), OB_WIN_MASK_LS(win_num)); ++ advk_writel(pcie, upper_32_bits(mask), OB_WIN_MASK_MS(win_num)); ++ advk_writel(pcie, actions, OB_WIN_ACTIONS(win_num)); ++} ++ ++static void advk_pcie_disable_ob_win(struct advk_pcie *pcie, u8 win_num) ++{ ++ advk_writel(pcie, 0, OB_WIN_MATCH_LS(win_num)); ++ advk_writel(pcie, 0, OB_WIN_MATCH_MS(win_num)); ++ advk_writel(pcie, 0, OB_WIN_REMAP_LS(win_num)); ++ advk_writel(pcie, 0, OB_WIN_REMAP_MS(win_num)); ++ advk_writel(pcie, 0, OB_WIN_MASK_LS(win_num)); ++ advk_writel(pcie, 0, OB_WIN_MASK_MS(win_num)); ++ advk_writel(pcie, 0, OB_WIN_ACTIONS(win_num)); ++} ++ + static void advk_pcie_setup_hw(struct advk_pcie *pcie) + { + u32 reg; ++ int i; + + /* Set to Direct mode */ + reg = advk_readl(pcie, CTRL_CONFIG_REG); +@@ -374,16 +451,52 @@ static void advk_pcie_setup_hw(struct ad + reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK); + advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG); + ++ /* ++ * Enable AXI address window location generation: ++ * When it is enabled, the default outbound window ++ * configurations (Default User Field: 0xD0074CFC) ++ * are used to transparent address translation for ++ * the outbound transactions. Thus, PCIe address ++ * windows are not required for transparent memory ++ * access when default outbound window configuration ++ * is set for memory access. ++ */ + reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); + reg |= PCIE_CORE_CTRL2_OB_WIN_ENABLE; + advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); + +- /* Bypass the address window mapping for PIO */ ++ /* ++ * Set memory access in Default User Field so it ++ * is not required to configure PCIe address for ++ * transparent memory access. ++ */ ++ advk_writel(pcie, OB_WIN_TYPE_MEM, OB_WIN_DEFAULT_ACTIONS); ++ ++ /* ++ * Bypass the address window mapping for PIO: ++ * Since PIO access already contains all required ++ * info over AXI interface by PIO registers, the ++ * address window is not required. ++ */ + reg = advk_readl(pcie, PIO_CTRL); + reg |= PIO_CTRL_ADDR_WIN_DISABLE; + advk_writel(pcie, reg, PIO_CTRL); + + /* ++ * Configure PCIe address windows for non-memory or ++ * non-transparent access as by default PCIe uses ++ * transparent memory access. ++ */ ++ for (i = 0; i < pcie->wins_count; i++) ++ advk_pcie_set_ob_win(pcie, i, ++ pcie->wins[i].match, pcie->wins[i].remap, ++ pcie->wins[i].mask, pcie->wins[i].actions); ++ ++ /* Disable remaining PCIe outbound windows */ ++ for (i = pcie->wins_count; i < OB_WIN_COUNT; i++) ++ advk_pcie_disable_ob_win(pcie, i); ++ ++ /* + * PERST# signal could have been asserted by pinctrl subsystem before + * probe() callback has been called, making the endpoint going into + * fundamental reset. As required by PCI Express spec a delay for at +@@ -1000,6 +1113,7 @@ static int advk_pcie_probe(struct platfo + struct resource *res; + struct pci_bus *bus, *child; + struct pci_host_bridge *bridge; ++ struct resource_entry *entry; + int ret, irq; + + bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie)); +@@ -1009,6 +1123,80 @@ static int advk_pcie_probe(struct platfo + pcie = pci_host_bridge_priv(bridge); + pcie->pdev = pdev; + ++ resource_list_for_each_entry(entry, &bridge->windows) { ++ resource_size_t start = entry->res->start; ++ resource_size_t size = resource_size(entry->res); ++ unsigned long type = resource_type(entry->res); ++ u64 win_size; ++ ++ /* ++ * Aardvark hardware allows to configure also PCIe window ++ * for config type 0 and type 1 mapping, but driver uses ++ * only PIO for issuing configuration transfers which does ++ * not use PCIe window configuration. ++ */ ++ if (type != IORESOURCE_MEM && type != IORESOURCE_MEM_64 && ++ type != IORESOURCE_IO) ++ continue; ++ ++ /* ++ * Skip transparent memory resources. Default outbound access ++ * configuration is set to transparent memory access so it ++ * does not need window configuration. ++ */ ++ if ((type == IORESOURCE_MEM || type == IORESOURCE_MEM_64) && ++ entry->offset == 0) ++ continue; ++ ++ /* ++ * The n-th PCIe window is configured by tuple (match, remap, mask) ++ * and an access to address A uses this window if A matches the ++ * match with given mask. ++ * So every PCIe window size must be a power of two and every start ++ * address must be aligned to window size. Minimal size is 64 KiB ++ * because lower 16 bits of mask must be zero. Remapped address ++ * may have set only bits from the mask. ++ */ ++ while (pcie->wins_count < OB_WIN_COUNT && size > 0) { ++ /* Calculate the largest aligned window size */ ++ win_size = (1ULL << (fls64(size)-1)) | ++ (start ? (1ULL << __ffs64(start)) : 0); ++ win_size = 1ULL << __ffs64(win_size); ++ if (win_size < 0x10000) ++ break; ++ ++ dev_dbg(dev, ++ "Configuring PCIe window %d: [0x%llx-0x%llx] as %lu\n", ++ pcie->wins_count, (unsigned long long)start, ++ (unsigned long long)start + win_size, type); ++ ++ if (type == IORESOURCE_IO) { ++ pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_IO; ++ pcie->wins[pcie->wins_count].match = pci_pio_to_address(start); ++ } else { ++ pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_MEM; ++ pcie->wins[pcie->wins_count].match = start; ++ } ++ pcie->wins[pcie->wins_count].remap = start - entry->offset; ++ pcie->wins[pcie->wins_count].mask = ~(win_size - 1); ++ ++ if (pcie->wins[pcie->wins_count].remap & (win_size - 1)) ++ break; ++ ++ start += win_size; ++ size -= win_size; ++ pcie->wins_count++; ++ } ++ ++ if (size > 0) { ++ dev_err(&pcie->pdev->dev, ++ "Invalid PCIe region [0x%llx-0x%llx]\n", ++ (unsigned long long)entry->res->start, ++ (unsigned long long)entry->res->end + 1); ++ return -EINVAL; ++ } ++ } ++ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pcie->base = devm_ioremap_resource(dev, res); + if (IS_ERR(pcie->base)) diff --git a/patches.suse/PCI-aardvark-Fix-PCIe-Max-Payload-Size-setting.patch b/patches.suse/PCI-aardvark-Fix-PCIe-Max-Payload-Size-setting.patch new file mode 100644 index 0000000..ab9c299 --- /dev/null +++ b/patches.suse/PCI-aardvark-Fix-PCIe-Max-Payload-Size-setting.patch @@ -0,0 +1,48 @@ +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= +Date: Tue, 5 Oct 2021 20:09:41 +0200 +Subject: PCI: aardvark: Fix PCIe Max Payload Size setting +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit +Git-commit: a4e17d65dafdd3513042d8f00404c9b6068a825c +Patch-mainline: 5.16-rc1 +References: git-fixes + +Change PCIe Max Payload Size setting in PCIe Device Control register to 512 +bytes to align with PCIe Link Initialization sequence as defined in Marvell +Armada 3700 Functional Specification. According to the specification, +maximal Max Payload Size supported by this device is 512 bytes. + +Without this kernel prints suspicious line: + + pci 0000:01:00.0: Upstream bridge's Max Payload Size set to 256 (was 16384, max 512) + +With this change it changes to: + + pci 0000:01:00.0: Upstream bridge's Max Payload Size set to 256 (was 512, max 512) + +[js] 4.12 uses old macros, so use 2 instead of 7 (0xe0 -> 0x40) + +Link: https://lore.kernel.org/r/20211005180952.6812-3-kabel@kernel.org +Fixes: 8c39d710363c ("PCI: aardvark: Add Aardvark PCI host controller driver") +Signed-off-by: Pali Rohár +Signed-off-by: Marek Behún +Signed-off-by: Lorenzo Pieralisi +Reviewed-by: Marek Behún +Cc: stable@vger.kernel.org +Signed-off-by: Jiri Slaby +--- + drivers/pci/host/pci-aardvark.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/pci/host/pci-aardvark.c ++++ b/drivers/pci/host/pci-aardvark.c +@@ -411,7 +411,7 @@ static void advk_pcie_setup_hw(struct ad + + /* Set PCIe Device Control and Status 1 PF0 register */ + reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE | +- (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) | ++ (2 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) | + PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE | + (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ << + PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT); diff --git a/patches.suse/PCI-aardvark-Fix-checking-for-PIO-status.patch b/patches.suse/PCI-aardvark-Fix-checking-for-PIO-status.patch new file mode 100644 index 0000000..a727028 --- /dev/null +++ b/patches.suse/PCI-aardvark-Fix-checking-for-PIO-status.patch @@ -0,0 +1,160 @@ +From: Evan Wang +Date: Thu, 22 Jul 2021 16:40:38 +0200 +Subject: PCI: aardvark: Fix checking for PIO status +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit +Git-commit: fcb461e2bc8b83b7eaca20cb2221e8b940f2189c +Patch-mainline: 5.15-rc1 +References: git-fixes + +There is an issue that when PCIe switch is connected to an Armada 3700 +board, there will be lots of warnings about PIO errors when reading the +config space. According to Aardvark PIO read and write sequence in HW +specification, the current way to check PIO status has the following +issues: + +1) For PIO read operation, it reports the error message, which should be + avoided according to HW specification. + +2) For PIO read and write operations, it only checks PIO operation complete + status, which is not enough, and error status should also be checked. + +This patch aligns the code with Aardvark PIO read and write sequence in HW +specification on PIO status check and fix the warnings when reading config +space. + +[pali: Fix CRS handling when CRSSVE is not enabled] + +Link: https://lore.kernel.org/r/20210722144041.12661-2-pali@kernel.org +Tested-by: Victor Gu +Signed-off-by: Evan Wang +Signed-off-by: Pali Rohár +Signed-off-by: Lorenzo Pieralisi +Reviewed-by: Victor Gu +Reviewed-by: Marek Behún +Cc: stable@vger.kernel.org # b1bd5714472c ("PCI: aardvark: Indicate error in 'val' when config read fails") +Signed-off-by: Jiri Slaby +--- + drivers/pci/host/pci-aardvark.c | 62 ++++++++++++++++++++++++++++++++++------ + 1 file changed, 54 insertions(+), 8 deletions(-) + +--- a/drivers/pci/host/pci-aardvark.c ++++ b/drivers/pci/host/pci-aardvark.c +@@ -57,6 +57,7 @@ + #define PIO_COMPLETION_STATUS_CRS 2 + #define PIO_COMPLETION_STATUS_CA 4 + #define PIO_NON_POSTED_REQ BIT(10) ++#define PIO_ERR_STATUS BIT(11) + #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8) + #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc) + #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10) +@@ -399,7 +400,7 @@ static void advk_pcie_setup_hw(struct ad + advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); + } + +-static void advk_pcie_check_pio_status(struct advk_pcie *pcie) ++static int advk_pcie_check_pio_status(struct advk_pcie *pcie, u32 *val) + { + struct device *dev = &pcie->pdev->dev; + u32 reg; +@@ -410,14 +411,49 @@ static void advk_pcie_check_pio_status(s + status = (reg & PIO_COMPLETION_STATUS_MASK) >> + PIO_COMPLETION_STATUS_SHIFT; + +- if (!status) +- return; +- ++ /* ++ * According to HW spec, the PIO status check sequence as below: ++ * 1) even if COMPLETION_STATUS(bit9:7) indicates successful, ++ * it still needs to check Error Status(bit11), only when this bit ++ * indicates no error happen, the operation is successful. ++ * 2) value Unsupported Request(1) of COMPLETION_STATUS(bit9:7) only ++ * means a PIO write error, and for PIO read it is successful with ++ * a read value of 0xFFFFFFFF. ++ * 3) value Completion Retry Status(CRS) of COMPLETION_STATUS(bit9:7) ++ * only means a PIO write error, and for PIO read it is successful ++ * with a read value of 0xFFFF0001. ++ * 4) value Completer Abort (CA) of COMPLETION_STATUS(bit9:7) means ++ * error for both PIO read and PIO write operation. ++ * 5) other errors are indicated as 'unknown'. ++ */ + switch (status) { ++ case PIO_COMPLETION_STATUS_OK: ++ if (reg & PIO_ERR_STATUS) { ++ strcomp_status = "COMP_ERR"; ++ break; ++ } ++ /* Get the read result */ ++ if (val) ++ *val = advk_readl(pcie, PIO_RD_DATA); ++ /* No error */ ++ strcomp_status = NULL; ++ break; + case PIO_COMPLETION_STATUS_UR: + strcomp_status = "UR"; + break; + case PIO_COMPLETION_STATUS_CRS: ++ /* PCIe r4.0, sec 2.3.2, says: ++ * If CRS Software Visibility is not enabled, the Root Complex ++ * must re-issue the Configuration Request as a new Request. ++ * A Root Complex implementation may choose to limit the number ++ * of Configuration Request/CRS Completion Status loops before ++ * determining that something is wrong with the target of the ++ * Request and taking appropriate action, e.g., complete the ++ * Request to the host as a failed transaction. ++ * ++ * To simplify implementation do not re-issue the Configuration ++ * Request and complete the Request as a failed transaction. ++ */ + strcomp_status = "CRS"; + break; + case PIO_COMPLETION_STATUS_CA: +@@ -428,6 +464,9 @@ static void advk_pcie_check_pio_status(s + break; + } + ++ if (!strcomp_status) ++ return 0; ++ + if (reg & PIO_NON_POSTED_REQ) + str_posted = "Non-posted"; + else +@@ -435,6 +474,8 @@ static void advk_pcie_check_pio_status(s + + dev_err(dev, "%s PIO Response Status: %s, %#x @ %#x\n", + str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS)); ++ ++ return -EFAULT; + } + + static int advk_pcie_wait_pio(struct advk_pcie *pcie) +@@ -545,10 +586,13 @@ static int advk_pcie_rd_conf(struct pci_ + return PCIBIOS_SET_FAILED; + } + +- advk_pcie_check_pio_status(pcie); ++ /* Check PIO status and get the read result */ ++ ret = advk_pcie_check_pio_status(pcie, val); ++ if (ret < 0) { ++ *val = 0xffffffff; ++ return PCIBIOS_SET_FAILED; ++ } + +- /* Get the read result */ +- *val = advk_readl(pcie, PIO_RD_DATA); + if (size == 1) + *val = (*val >> (8 * (where & 3))) & 0xff; + else if (size == 2) +@@ -608,7 +652,9 @@ static int advk_pcie_wr_conf(struct pci_ + if (ret < 0) + return PCIBIOS_SET_FAILED; + +- advk_pcie_check_pio_status(pcie); ++ ret = advk_pcie_check_pio_status(pcie, NULL); ++ if (ret < 0) ++ return PCIBIOS_SET_FAILED; + + return PCIBIOS_SUCCESSFUL; + } diff --git a/patches.suse/PCI-aardvark-Fix-masking-and-unmasking-legacy-INTx-i.patch b/patches.suse/PCI-aardvark-Fix-masking-and-unmasking-legacy-INTx-i.patch new file mode 100644 index 0000000..c2e8993 --- /dev/null +++ b/patches.suse/PCI-aardvark-Fix-masking-and-unmasking-legacy-INTx-i.patch @@ -0,0 +1,73 @@ +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= +Date: Fri, 20 Aug 2021 17:50:20 +0200 +Subject: PCI: aardvark: Fix masking and unmasking legacy INTx interrupts +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit +Git-commit: d212dcee27c1f89517181047e5485fcbba4a25c2 +Patch-mainline: 5.15-rc1 +References: git-fixes + +irq_mask and irq_unmask callbacks need to be properly guarded by raw spin +locks as masking/unmasking procedure needs atomic read-modify-write +operation on hardware register. + +Link: https://lore.kernel.org/r/20210820155020.3000-1-pali@kernel.org +Reported-by: Marc Zyngier +Signed-off-by: Pali Rohár +Signed-off-by: Lorenzo Pieralisi +Acked-by: Marc Zyngier +Cc: stable@vger.kernel.org +Signed-off-by: Jiri Slaby +--- + drivers/pci/host/pci-aardvark.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/drivers/pci/host/pci-aardvark.c ++++ b/drivers/pci/host/pci-aardvark.c +@@ -231,6 +231,7 @@ struct advk_pcie { + u8 wins_count; + struct irq_domain *irq_domain; + struct irq_chip irq_chip; ++ raw_spinlock_t irq_lock; + struct irq_domain *msi_domain; + struct irq_domain *msi_inner_domain; + struct irq_chip msi_bottom_irq_chip; +@@ -841,22 +842,28 @@ static void advk_pcie_irq_mask(struct ir + { + struct advk_pcie *pcie = d->domain->host_data; + irq_hw_number_t hwirq = irqd_to_hwirq(d); ++ unsigned long flags; + u32 mask; + ++ raw_spin_lock_irqsave(&pcie->irq_lock, flags); + mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); + mask |= PCIE_ISR1_INTX_ASSERT(hwirq); + advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); ++ raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); + } + + static void advk_pcie_irq_unmask(struct irq_data *d) + { + struct advk_pcie *pcie = d->domain->host_data; + irq_hw_number_t hwirq = irqd_to_hwirq(d); ++ unsigned long flags; + u32 mask; + ++ raw_spin_lock_irqsave(&pcie->irq_lock, flags); + mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); + mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq); + advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); ++ raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); + } + + static int advk_pcie_irq_map(struct irq_domain *h, +@@ -940,6 +947,8 @@ static int advk_pcie_init_irq_domain(str + struct irq_chip *irq_chip; + int ret = 0; + ++ raw_spin_lock_init(&pcie->irq_lock); ++ + pcie_intc_node = of_get_next_child(node, NULL); + if (!pcie_intc_node) { + dev_err(dev, "No PCIe Intc node found\n"); diff --git a/patches.suse/PCI-aardvark-Increase-polling-delay-to-1.5s-while-wa.patch b/patches.suse/PCI-aardvark-Increase-polling-delay-to-1.5s-while-wa.patch new file mode 100644 index 0000000..5c99f31 --- /dev/null +++ b/patches.suse/PCI-aardvark-Increase-polling-delay-to-1.5s-while-wa.patch @@ -0,0 +1,54 @@ +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= +Date: Thu, 22 Jul 2021 16:40:39 +0200 +Subject: PCI: aardvark: Increase polling delay to 1.5s while waiting for PIO + response +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit +Git-commit: 02bcec3ea5591720114f586960490b04b093a09e +Patch-mainline: 5.15-rc1 +References: git-fixes + +Measurements in different conditions showed that aardvark hardware PIO +response can take up to 1.44s. Increase wait timeout from 1ms to 1.5s to +ensure that we do not miss responses from hardware. After 1.44s hardware +returns errors (e.g. Completer abort). + +The previous two patches fixed checking for PIO status, so now we can use +it to also catch errors which are reported by hardware after 1.44s. + +After applying this patch, kernel can detect and print PIO errors to dmesg: + + [ 6.879999] advk-pcie d0070000.pcie: Non-posted PIO Response Status: CA, 0xe00 @ 0x100004 + [ 6.896436] advk-pcie d0070000.pcie: Posted PIO Response Status: COMP_ERR, 0x804 @ 0x100004 + [ 6.913049] advk-pcie d0070000.pcie: Posted PIO Response Status: COMP_ERR, 0x804 @ 0x100010 + [ 6.929663] advk-pcie d0070000.pcie: Non-posted PIO Response Status: CA, 0xe00 @ 0x100010 + [ 6.953558] advk-pcie d0070000.pcie: Posted PIO Response Status: COMP_ERR, 0x804 @ 0x100014 + [ 6.970170] advk-pcie d0070000.pcie: Non-posted PIO Response Status: CA, 0xe00 @ 0x100014 + [ 6.994328] advk-pcie d0070000.pcie: Posted PIO Response Status: COMP_ERR, 0x804 @ 0x100004 + +Without this patch kernel prints only a generic error to dmesg: + + [ 5.246847] advk-pcie d0070000.pcie: config read/write timed out + +Link: https://lore.kernel.org/r/20210722144041.12661-3-pali@kernel.org +Signed-off-by: Pali Rohár +Signed-off-by: Lorenzo Pieralisi +Reviewed-by: Marek Behún +Cc: stable@vger.kernel.org # 7fbcb5da811b ("PCI: aardvark: Don't rely on jiffies while holding spinlock") +Signed-off-by: Jiri Slaby +--- + drivers/pci/host/pci-aardvark.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/pci/host/pci-aardvark.c ++++ b/drivers/pci/host/pci-aardvark.c +@@ -169,7 +169,7 @@ + (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \ + PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where)) + +-#define PIO_RETRY_CNT 500 ++#define PIO_RETRY_CNT 750000 /* 1.5 s */ + #define PIO_RETRY_DELAY 2 /* 2 us*/ + + #define LINK_WAIT_MAX_RETRIES 10 diff --git a/patches.suse/PCI-xilinx-nwl-Enable-the-clock-through-CCF.patch b/patches.suse/PCI-xilinx-nwl-Enable-the-clock-through-CCF.patch new file mode 100644 index 0000000..24c4771 --- /dev/null +++ b/patches.suse/PCI-xilinx-nwl-Enable-the-clock-through-CCF.patch @@ -0,0 +1,60 @@ +From: Hyun Kwon +Date: Fri, 25 Jun 2021 12:48:23 +0200 +Subject: PCI: xilinx-nwl: Enable the clock through CCF +Git-commit: de0a01f5296651d3a539f2d23d0db8f359483696 +Patch-mainline: 5.15-rc1 +References: git-fixes + +Enable PCIe reference clock. There is no remove function that's why +this should be enough for simple operation. +Normally this clock is enabled by default by firmware but there are +usecases where this clock should be enabled by driver itself. +It is also good that PCIe clock is recorded in a clock framework. + +Link: https://lore.kernel.org/r/ee6997a08fab582b1c6de05f8be184f3fe8d5357.1624618100.git.michal.simek@xilinx.com +Fixes: ab597d35ef11 ("PCI: xilinx-nwl: Add support for Xilinx NWL PCIe Host Controller") +Signed-off-by: Hyun Kwon +Signed-off-by: Bharat Kumar Gogada +Signed-off-by: Michal Simek +Signed-off-by: Lorenzo Pieralisi +Cc: stable@vger.kernel.org +Signed-off-by: Jiri Slaby +--- + drivers/pci/host/pcie-xilinx-nwl.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/drivers/pci/host/pcie-xilinx-nwl.c ++++ b/drivers/pci/host/pcie-xilinx-nwl.c +@@ -10,6 +10,7 @@ + * (at your option) any later version. + */ + ++#include + #include + #include + #include +@@ -171,6 +172,7 @@ struct nwl_pcie { + u8 root_busno; + struct nwl_msi msi; + struct irq_domain *legacy_irq_domain; ++ struct clk *clk; + }; + + static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off) +@@ -808,6 +810,16 @@ static int nwl_pcie_probe(struct platfor + return err; + } + ++ pcie->clk = devm_clk_get(dev, NULL); ++ if (IS_ERR(pcie->clk)) ++ return PTR_ERR(pcie->clk); ++ ++ err = clk_prepare_enable(pcie->clk); ++ if (err) { ++ dev_err(dev, "can't enable PCIe ref clock\n"); ++ return err; ++ } ++ + err = nwl_pcie_bridge_init(pcie); + if (err) { + dev_err(dev, "HW Initialization failed\n"); diff --git a/patches.suse/ipv4-ipv4_default_advmss-should-use-route-mtu.patch b/patches.suse/ipv4-ipv4_default_advmss-should-use-route-mtu.patch new file mode 100644 index 0000000..354a5f1 --- /dev/null +++ b/patches.suse/ipv4-ipv4_default_advmss-should-use-route-mtu.patch @@ -0,0 +1,35 @@ +From ce720f2e5375229e2bdcb44424b185f30dae25b6 Mon Sep 17 00:00:00 2001 +From: Eric Dumazet +Date: Wed, 18 Oct 2017 17:02:03 -0700 +Subject: [PATCH 2/7] ipv4: ipv4_default_advmss() should use route mtu +Git-commit: 164a5e7ad531e181334a3d3f03d0d5ad20d6faea +Patch-mainline: 4.15-rc1 +References: git-fixes + +ipv4_default_advmss() incorrectly uses the device MTU instead +of the route provided one. IPv6 has the proper behavior, +lets harmonize the two protocols. + +Signed-off-by: Eric Dumazet +Signed-off-by: David S. Miller +Signed-off-by: Denis Kirjanov +--- + net/ipv4/route.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/net/ipv4/route.c b/net/ipv4/route.c +index e55ec9708d88..87671aa02fd5 100644 +--- a/net/ipv4/route.c ++++ b/net/ipv4/route.c +@@ -1319,7 +1319,7 @@ static void set_class_tag(struct rtable *rt, u32 tag) + static unsigned int ipv4_default_advmss(const struct dst_entry *dst) + { + unsigned int header_size = sizeof(struct tcphdr) + sizeof(struct iphdr); +- unsigned int advmss = max_t(unsigned int, dst->dev->mtu - header_size, ++ unsigned int advmss = max_t(unsigned int, ipv4_mtu(dst) - header_size, + ip_rt_min_advmss); + + return min(advmss, IPV4_MAX_PMTU - header_size); +-- +2.16.4 + diff --git a/patches.suse/ipv6-Reinject-IPv6-packets-if-IPsec-policy-matches-a.patch b/patches.suse/ipv6-Reinject-IPv6-packets-if-IPsec-policy-matches-a.patch new file mode 100644 index 0000000..240e366 --- /dev/null +++ b/patches.suse/ipv6-Reinject-IPv6-packets-if-IPsec-policy-matches-a.patch @@ -0,0 +1,44 @@ +From 7c90b6940754463f9245305e7864a129a0a500d6 Mon Sep 17 00:00:00 2001 +From: Tobias Brunner +Date: Thu, 21 Dec 2017 17:32:24 +0100 +Subject: [PATCH 6/7] ipv6: Reinject IPv6 packets if IPsec policy matches after + SNAT +Git-commit: 09ee9dba9611cd382fd360a99ad1c2fa23bfdca8 +Patch-mainline: 4.16-rc1 +References: git-fixes + +If SNAT modifies the source address the resulting packet might match +an IPsec policy, reinject the packet if that's the case. + +The exact same thing is already done for IPv4. + +Signed-off-by: Tobias Brunner +Acked-by: Steffen Klassert +Signed-off-by: David S. Miller +Signed-off-by: Denis Kirjanov +--- + net/ipv6/ip6_output.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/net/ipv6/ip6_output.c b/net/ipv6/ip6_output.c +index 50fed3140aa1..4657b1f76b2b 100644 +--- a/net/ipv6/ip6_output.c ++++ b/net/ipv6/ip6_output.c +@@ -141,6 +141,14 @@ static int ip6_finish_output(struct net *net, struct sock *sk, struct sk_buff *s + return ret; + } + ++#if defined(CONFIG_NETFILTER) && defined(CONFIG_XFRM) ++ /* Policy lookup after SNAT yielded a new policy */ ++ if (skb_dst(skb)->xfrm) { ++ IPCB(skb)->flags |= IPSKB_REROUTED; ++ return dst_output(net, sk, skb); ++ } ++#endif ++ + if ((skb->len > ip6_skb_dst_mtu(skb) && !skb_is_gso(skb)) || + dst_allfrag(skb_dst(skb)) || + (IP6CB(skb)->frag_max_size && skb->len > IP6CB(skb)->frag_max_size)) +-- +2.16.4 + diff --git a/patches.suse/ipv6-icmp6-Allow-icmp-messages-to-be-looped-back.patch b/patches.suse/ipv6-icmp6-Allow-icmp-messages-to-be-looped-back.patch new file mode 100644 index 0000000..17534f0 --- /dev/null +++ b/patches.suse/ipv6-icmp6-Allow-icmp-messages-to-be-looped-back.patch @@ -0,0 +1,46 @@ +From 55f8e57a05126a75c87b1386e1cf85c496ff2996 Mon Sep 17 00:00:00 2001 +From: Brendan McGrath +Date: Wed, 13 Dec 2017 22:14:57 +1100 +Subject: [PATCH 3/7] ipv6: icmp6: Allow icmp messages to be looped back +Git-commit: 588753f1eb18978512b1c9b85fddb457d46f9033 +Patch-mainline: 4.15-rc5 +References: git-fixes + +One example of when an ICMPv6 packet is required to be looped back is +when a host acts as both a Multicast Listener and a Multicast Router. + +A Multicast Router will listen on address ff02::16 for MLDv2 messages. + +Currently, MLDv2 messages originating from a Multicast Listener running +on the same host as the Multicast Router are not being delivered to the +Multicast Router. This is due to dst.input being assigned the default +value of dst_discard. + +This results in the packet being looped back but discarded before being +delivered to the Multicast Router. + +This patch sets dst.input to ip6_input to ensure a looped back packet +is delivered to the Multicast Router. + +Signed-off-by: Brendan McGrath +Signed-off-by: David S. Miller +Signed-off-by: Denis Kirjanov +--- + net/ipv6/route.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/net/ipv6/route.c b/net/ipv6/route.c +index ff1c0fbc4a5e..2990fcf19878 100644 +--- a/net/ipv6/route.c ++++ b/net/ipv6/route.c +@@ -1682,6 +1682,7 @@ struct dst_entry *icmp6_dst_alloc(struct net_device *dev, + } + + rt->dst.flags |= DST_HOST; ++ rt->dst.input = ip6_input; + rt->dst.output = ip6_output; + rt->rt6i_gateway = fl6->daddr; + rt->rt6i_dst.addr = fl6->daddr; +-- +2.16.4 + diff --git a/patches.suse/net-ipv6-send-NS-for-DAD-when-link-operationally-up.patch b/patches.suse/net-ipv6-send-NS-for-DAD-when-link-operationally-up.patch new file mode 100644 index 0000000..245820a --- /dev/null +++ b/patches.suse/net-ipv6-send-NS-for-DAD-when-link-operationally-up.patch @@ -0,0 +1,75 @@ +From 1ade0662e2dc7c31c701e384a0d6da0971e235a8 Mon Sep 17 00:00:00 2001 +From: Mike Manning +Date: Mon, 25 Sep 2017 22:01:36 +0100 +Subject: [PATCH 1/7] net: ipv6: send NS for DAD when link operationally up +Git-commit: 1f372c7bfb23286d2bf4ce0423ab488e86b74bb2 +Patch-mainline: 4.15-rc1 +References: git-fixes + +The NS for DAD are sent on admin up as long as a valid qdisc is found. +A race condition exists by which these packets will not egress the +interface if the operational state of the lower device is not yet up. +The solution is to delay DAD until the link is operationally up +according to RFC2863. Rather than only doing this, follow the existing +code checks by deferring IPv6 device initialization altogether. The fix +allows DAD on devices like tunnels that are controlled by userspace +control plane. The fix has no impact on regular deployments, but means +that there is no IPv6 connectivity until the port has been opened in +the case of port-based network access control, which should be +desirable. + +Signed-off-by: Mike Manning +Signed-off-by: David S. Miller +Signed-off-by: Denis Kirjanov +--- + net/ipv6/addrconf.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/net/ipv6/addrconf.c b/net/ipv6/addrconf.c +index fc7dae23c492..67ddc0d22609 100644 +--- a/net/ipv6/addrconf.c ++++ b/net/ipv6/addrconf.c +@@ -304,10 +304,10 @@ static struct ipv6_devconf ipv6_devconf_dflt __read_mostly = { + .disable_policy = 0, + }; + +-/* Check if a valid qdisc is available */ +-static inline bool addrconf_qdisc_ok(const struct net_device *dev) ++/* Check if link is ready: is it up and is a valid qdisc available */ ++static inline bool addrconf_link_ready(const struct net_device *dev) + { +- return !qdisc_tx_is_noop(dev); ++ return netif_oper_up(dev) && !qdisc_tx_is_noop(dev); + } + + static void addrconf_del_rs_timer(struct inet6_dev *idev) +@@ -450,7 +450,7 @@ static struct inet6_dev *ipv6_add_dev(struct net_device *dev) + + ndev->token = in6addr_any; + +- if (netif_running(dev) && addrconf_qdisc_ok(dev)) ++ if (netif_running(dev) && addrconf_link_ready(dev)) + ndev->if_flags |= IF_READY; + + ipv6_mc_init_dev(ndev); +@@ -3482,7 +3482,7 @@ static int addrconf_notify(struct notifier_block *this, unsigned long event, + /* restore routes for permanent addresses */ + addrconf_permanent_addr(dev); + +- if (!addrconf_qdisc_ok(dev)) { ++ if (!addrconf_link_ready(dev)) { + /* device is not ready yet. */ + pr_info("ADDRCONF(NETDEV_UP): %s: link is not ready\n", + dev->name); +@@ -3497,7 +3497,7 @@ static int addrconf_notify(struct notifier_block *this, unsigned long event, + run_pending = 1; + } + } else if (event == NETDEV_CHANGE) { +- if (!addrconf_qdisc_ok(dev)) { ++ if (!addrconf_link_ready(dev)) { + /* device is still not ready. */ + break; + } +-- +2.16.4 + diff --git a/patches.suse/sctp-make-use-of-pre-calculated-len.patch b/patches.suse/sctp-make-use-of-pre-calculated-len.patch new file mode 100644 index 0000000..1fa20c0 --- /dev/null +++ b/patches.suse/sctp-make-use-of-pre-calculated-len.patch @@ -0,0 +1,96 @@ +From b1eef66295a6c4f4f42b235592b339a8fa0d067c Mon Sep 17 00:00:00 2001 +From: Marcelo Ricardo Leitner +Date: Mon, 8 Jan 2018 19:02:29 -0200 +Subject: [PATCH 5/7] sctp: make use of pre-calculated len +Git-commit: c76f97c99ae6d26d14c7f0e50e074382bfbc9f98 +Patch-mainline: 4.15-rc8 +References: git-fixes + +Some sockopt handling functions were calculating the length of the +buffer to be written to userspace and then calculating it again when +actually writing the buffer, which could lead to some write not using +an up-to-date length. + +This patch updates such places to just make use of the len variable. + +Also, replace some sizeof(type) to sizeof(var). + +Signed-off-by: Marcelo Ricardo Leitner +Signed-off-by: David S. Miller +Signed-off-by: Denis Kirjanov +--- + net/sctp/socket.c | 16 ++++++++++------ + 1 file changed, 10 insertions(+), 6 deletions(-) + +diff --git a/net/sctp/socket.c b/net/sctp/socket.c +index 4713dd8f5ecf..7e2914216f0f 100644 +--- a/net/sctp/socket.c ++++ b/net/sctp/socket.c +@@ -4983,7 +4983,7 @@ static int sctp_getsockopt_autoclose(struct sock *sk, int len, char __user *optv + len = sizeof(int); + if (put_user(len, optlen)) + return -EFAULT; +- if (copy_to_user(optval, &sctp_sk(sk)->autoclose, sizeof(int))) ++ if (copy_to_user(optval, &sctp_sk(sk)->autoclose, len)) + return -EFAULT; + return 0; + } +@@ -5560,6 +5560,9 @@ static int sctp_getsockopt_local_addrs(struct sock *sk, int len, + err = -EFAULT; + goto out; + } ++ /* XXX: We should have accounted for sizeof(struct sctp_getaddrs) too, ++ * but we can't change it anymore. ++ */ + if (put_user(bytes_copied, optlen)) + err = -EFAULT; + out: +@@ -5996,7 +5999,7 @@ static int sctp_getsockopt_maxseg(struct sock *sk, int len, + params.assoc_id = 0; + } else if (len >= sizeof(struct sctp_assoc_value)) { + len = sizeof(struct sctp_assoc_value); +- if (copy_from_user(¶ms, optval, sizeof(params))) ++ if (copy_from_user(¶ms, optval, len)) + return -EFAULT; + } else + return -EINVAL; +@@ -6165,7 +6168,9 @@ static int sctp_getsockopt_active_key(struct sock *sk, int len, + + if (len < sizeof(struct sctp_authkeyid)) + return -EINVAL; +- if (copy_from_user(&val, optval, sizeof(struct sctp_authkeyid))) ++ ++ len = sizeof(struct sctp_authkeyid); ++ if (copy_from_user(&val, optval, len)) + return -EFAULT; + + asoc = sctp_id2assoc(sk, val.scact_assoc_id); +@@ -6177,7 +6182,6 @@ static int sctp_getsockopt_active_key(struct sock *sk, int len, + else + val.scact_keynumber = ep->active_key_id; + +- len = sizeof(struct sctp_authkeyid); + if (put_user(len, optlen)) + return -EFAULT; + if (copy_to_user(optval, &val, len)) +@@ -6203,7 +6207,7 @@ static int sctp_getsockopt_peer_auth_chunks(struct sock *sk, int len, + if (len < sizeof(struct sctp_authchunks)) + return -EINVAL; + +- if (copy_from_user(&val, optval, sizeof(struct sctp_authchunks))) ++ if (copy_from_user(&val, optval, sizeof(val))) + return -EFAULT; + + to = p->gauth_chunks; +@@ -6248,7 +6252,7 @@ static int sctp_getsockopt_local_auth_chunks(struct sock *sk, int len, + if (len < sizeof(struct sctp_authchunks)) + return -EINVAL; + +- if (copy_from_user(&val, optval, sizeof(struct sctp_authchunks))) ++ if (copy_from_user(&val, optval, sizeof(val))) + return -EFAULT; + + to = p->gauth_chunks; +-- +2.16.4 + diff --git a/series.conf b/series.conf index 8eb2840..5529deb 100644 --- a/series.conf +++ b/series.conf @@ -13442,6 +13442,7 @@ patches.suse/bpf-libbpf-Provide-basic-API-support-to-specify-BPF-.patch patches.suse/bpf-Swap-the-order-of-checking-prog_info-and-map_inf.patch patches.suse/bpf-Test-new-fields-in-bpf_attr-and-bpf_-prog-map-_i.patch + patches.suse/net-ipv6-send-NS-for-DAD-when-link-operationally-up.patch patches.suse/i40e-i40evf-rename-bytes_per_int-to-bytes_per_usec.patch patches.suse/i40e-Fix-unqualified-module-message-while-bringing-l.patch patches.suse/i40e-Fix-link-down-message-when-interface-is-brought.patch @@ -13964,6 +13965,7 @@ patches.suse/bpf-Add-file-mode-configuration-into-bpf-maps.patch patches.suse/bpf-Add-tests-for-eBPF-file-mode.patch patches.suse/spectrum-Convert-fib-event-handlers-to-use-container.patch + patches.suse/ipv4-ipv4_default_advmss-should-use-route-mtu.patch patches.suse/Bluetooth-btqcomsmd-Add-support-for-BD-address-setup patches.suse/ieee802154-fix-gcc-4.9-warnings patches.suse/Bluetooth-hci_uart_set_flow_control-Fix-NULL-deref-w @@ -18861,6 +18863,7 @@ patches.suse/block-fix-blk_rq_append_bio.patch patches.suse/block-throttle-avoid-double-charge.patch patches.suse/0001-block-unalign-call_single_data-in-struct-request.patch + patches.suse/ipv6-icmp6-Allow-icmp-messages-to-be-looped-back.patch patches.suse/xdp-linearize-skb-in-netif_receive_generic_xdp.patch patches.suse/bpf-s390x-do-not-reload-skb-pointers-in-non-skb-cont.patch patches.suse/bpf-ppc64-do-not-reload-skb-pointers-in-non-skb-cont.patch @@ -19263,6 +19266,7 @@ patches.suse/bpf-avoid-false-sharing-of-map-refcount-with-max_ent.patch patches.suse/bpf-introduce-BPF_JIT_ALWAYS_ON-config.patch patches.suse/sctp-add-a-ceiling-to-optlen-in-some-sockopts.patch + patches.suse/sctp-make-use-of-pre-calculated-len.patch patches.suse/0001-net-gianfar_ptp-move-set_fipers-to-spinlock-protecti.patch patches.suse/0001-iwlwifi-pcie-fix-DMA-memory-mapping-unmapping.patch patches.suse/wcn36xx-Fix-dynamic-power-saving @@ -21322,6 +21326,7 @@ patches.suse/sfc-expose-FEC-stats-on-Medford2.patch patches.suse/sfc-expose-CTPIO-stats-on-NICs-that-support-them.patch patches.suse/enic-add-wq-clean-up-budget.patch + patches.suse/ipv6-Reinject-IPv6-packets-if-IPsec-policy-matches-a.patch patches.suse/net-hns3-add-support-to-query-tqps-number.patch patches.suse/net-hns3-add-support-to-modify-tqps-number.patch patches.suse/net-hns3-change-the-returned-tqp-number-by-ethtool-x.patch @@ -61597,7 +61602,16 @@ patches.suse/net-usb-cdc_mbim-avoid-altsetting-toggling-for-Telit.patch patches.suse/net-usb-qmi_wwan-add-Telit-0x1060-composition.patch patches.suse/qlcnic-Remove-redundant-unlock-in-qlcnic_pinit_from_.patch + patches.suse/PCI-Call-Max-Payload-Size-related-fixup-quirks-early.patch + patches.suse/PCI-Restrict-ASMedia-ASM1062-SATA-Max-Payload-Size-S.patch + patches.suse/PCI-Return-0-data-on-pciconfig_read-CAP_SYS_ADMIN-fa.patch + patches.suse/PCI-Add-ACS-quirks-for-Cavium-multi-function-devices.patch + patches.suse/PCI-aardvark-Fix-checking-for-PIO-status.patch + patches.suse/PCI-aardvark-Increase-polling-delay-to-1.5s-while-wa.patch + patches.suse/PCI-aardvark-Configure-PCIe-resources-from-ranges-DT.patch + patches.suse/PCI-aardvark-Fix-masking-and-unmasking-legacy-INTx-i.patch patches.suse/msft-hv-2426-PCI-hv-Support-for-create-interrupt-v3.patch + patches.suse/PCI-xilinx-nwl-Enable-the-clock-through-CCF.patch patches.suse/profiling-fix-shift-out-of-bounds-bugs.patch patches.suse/prctl-allow-to-setup-brk-for-et_dyn-executables.patch patches.suse/ceph-lockdep-annotations-for-try_nonblocking_invalidate.patch @@ -61884,7 +61898,9 @@ patches.suse/ocfs2-do-not-zero-pages-beyond-i_size.patch patches.suse/0001-memcg-kmem-further-deprecate-kmem.limit_in_bytes.patch patches.suse/0002-PCI-Do-not-enable-AtomicOps-on-VFs.patch + patches.suse/PCI-Mark-Atheros-QCA6174-to-avoid-bus-reset.patch patches.suse/msft-hv-2452-PCI-hv-Remove-unnecessary-use-of-hx.patch + patches.suse/PCI-aardvark-Fix-PCIe-Max-Payload-Size-setting.patch patches.suse/s390-cio-make-ccw_device_dma_-more-robust patches.suse/s390-pci-add-s390_iommu_aperture-kernel-parameter patches.suse/quota-check-block-number-when-reading-the-block-in-q.patch