From: Tarun Vyas Date: Wed, 11 Jul 2018 22:33:23 -0700 Subject: drm/i915: Use crtc_state->has_psr instead of CAN_PSR for pipe update Git-commit: c3d433617d2048f5fc3ee1135bce1a9bc2375662 Patch-mainline: v4.19-rc1 References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166 In commit "drm/i915: Wait for PSR exit before checking for vblank evasion", the idea was to limit the PSR IDLE checks when PSR is actually supported. While CAN_PSR does do that check, it doesn't applies on a per-crtc basis. crtc_state->has_psr is a more granular check that only applies to pipe(s) that have PSR enabled. Without the has_psr check, we end up waiting on the eDP transcoder's PSR_STATUS register irrespective of whether the pipe being updated is driving it or not. v2: Remove unnecessary parantheses, make checkpatch happy. v3: Move the has_psr check to intel_psr_wait_for_idle and commit message changes (DK). v4: Derive dev_priv from intel_crtc_state (DK) v5: Commit message changes to reflect the HW behavior (DK) Fixes: a608987970b9 ("drm/i915: Wait for PSR exit before checking for vblank evasion") Reviewed-by: Dhinakaran Pandiyan Signed-off-by: Tarun Vyas Signed-off-by: Dhinakaran Pandiyan Link: https://patchwork.freedesktop.org/patch/msgid/20180712053323.26266-1-tarun.vyas@intel.com Acked-by: Petr Tesarik --- drivers/gpu/drm/i915/intel_drv.h | 2 +- drivers/gpu/drm/i915/intel_psr.c | 7 ++++++- drivers/gpu/drm/i915/intel_sprite.c | 2 +- 3 files changed, 8 insertions(+), 3 deletions(-) --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1922,7 +1922,7 @@ void intel_psr_compute_config(struct int void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug); void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir); void intel_psr_short_pulse(struct intel_dp *intel_dp); -int intel_psr_wait_for_idle(struct drm_i915_private *dev_priv); +int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state); /* intel_runtime_pm.c */ int intel_power_domains_init(struct drm_i915_private *); --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -717,11 +717,16 @@ void intel_psr_disable(struct intel_dp * cancel_work_sync(&dev_priv->psr.work); } -int intel_psr_wait_for_idle(struct drm_i915_private *dev_priv) +int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state) { + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); i915_reg_t reg; u32 mask; + if (!new_crtc_state->has_psr) + return 0; + /* * The sole user right now is intel_pipe_update_start(), * which won't race with psr_enable/disable, which is --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -104,7 +104,7 @@ void intel_pipe_update_start(const struc * VBL interrupts will start the PSR exit and prevent a PSR * re-entry as well. */ - if (CAN_PSR(dev_priv) && intel_psr_wait_for_idle(dev_priv)) + if (intel_psr_wait_for_idle(new_crtc_state)) DRM_ERROR("PSR idle timed out, atomic update may fail\n"); local_irq_disable();