diff --git a/patches.suse/RDMA-hns-Fix-mis-modifying-default-congestion-contro.patch b/patches.suse/RDMA-hns-Fix-mis-modifying-default-congestion-contro.patch new file mode 100644 index 0000000..3bb3c29 --- /dev/null +++ b/patches.suse/RDMA-hns-Fix-mis-modifying-default-congestion-contro.patch @@ -0,0 +1,134 @@ +From d20a7cf9f714f0763efb56f0f2eeca1cb91315ed Mon Sep 17 00:00:00 2001 +From: Luoyouming +Date: Mon, 19 Feb 2024 14:18:05 +0800 +Subject: [PATCH 1/1] RDMA/hns: Fix mis-modifying default congestion control + algorithm +Git-commit: d20a7cf9f714f0763efb56f0f2eeca1cb91315ed +Patch-mainline: v6.9-rc1 +References: git-fixes + +Commit 27c5fd271d8b ("RDMA/hns: The UD mode can only be configured +with DCQCN") adds a check of congest control alorithm for UD. But +that patch causes a problem: hr_dev->caps.congest_type is global, +used by all QPs, so modifying this field to DCQCN for UD QPs causes +other QPs unable to use any other algorithm except DCQCN. + +Revert the modification in commit 27c5fd271d8b ("RDMA/hns: The UD +mode can only be configured with DCQCN"). Add a new field cong_type +to struct hns_roce_qp and configure DCQCN for UD QPs. + +Fixes: 27c5fd271d8b ("RDMA/hns: The UD mode can only be configured with DCQCN") +Fixes: f91696f2f053 ("RDMA/hns: Support congestion control type selection according to the FW") +Signed-off-by: Luoyouming +Signed-off-by: Junxian Huang +Link: https://lore.kernel.org/r/20240219061805.668170-1-huangjunxian6@hisilicon.com +Signed-off-by: Leon Romanovsky +Acked-by: Nicolas Morey +--- + drivers/infiniband/hw/hns/hns_roce_device.h | 17 +++++++++-------- + drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 16 ++++++++++------ + 2 files changed, 19 insertions(+), 14 deletions(-) + +diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniband/hw/hns/hns_roce_device.h +index 1a8516019516..1d062c522d69 100644 +--- a/drivers/infiniband/hw/hns/hns_roce_device.h ++++ b/drivers/infiniband/hw/hns/hns_roce_device.h +@@ -638,6 +638,13 @@ enum { + HNS_ROCE_QP_CAP_DIRECT_WQE = BIT(5), + }; + ++enum hns_roce_cong_type { ++ CONG_TYPE_DCQCN, ++ CONG_TYPE_LDCP, ++ CONG_TYPE_HC3, ++ CONG_TYPE_DIP, ++}; ++ + struct hns_roce_qp { + struct ib_qp ibqp; + struct hns_roce_wq rq; +@@ -682,6 +689,7 @@ struct hns_roce_qp { + struct list_head node; /* all qps are on a list */ + struct list_head rq_node; /* all recv qps are on a list */ + struct list_head sq_node; /* all send qps are on a list */ ++ enum hns_roce_cong_type cong_type; + }; + + struct hns_roce_ib_iboe { +@@ -750,13 +758,6 @@ struct hns_roce_eq_table { + void __iomem **eqc_base; /* only for hw v1 */ + }; + +-enum cong_type { +- CONG_TYPE_DCQCN, +- CONG_TYPE_LDCP, +- CONG_TYPE_HC3, +- CONG_TYPE_DIP, +-}; +- + struct hns_roce_caps { + u64 fw_ver; + u8 num_ports; +@@ -844,7 +845,7 @@ struct hns_roce_caps { + u16 default_aeq_period; + u16 default_aeq_arm_st; + u16 default_ceq_arm_st; +- enum cong_type cong_type; ++ enum hns_roce_cong_type cong_type; + }; + + struct hns_roce_dfx_hw { +diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c +index de56dc6e3226..42e28586cefa 100644 +--- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c ++++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c +@@ -4738,12 +4738,15 @@ static int check_cong_type(struct ib_qp *ibqp, + struct hns_roce_congestion_algorithm *cong_alg) + { + struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); ++ struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); + +- if (ibqp->qp_type == IB_QPT_UD) +- hr_dev->caps.cong_type = CONG_TYPE_DCQCN; ++ if (ibqp->qp_type == IB_QPT_UD || ibqp->qp_type == IB_QPT_GSI) ++ hr_qp->cong_type = CONG_TYPE_DCQCN; ++ else ++ hr_qp->cong_type = hr_dev->caps.cong_type; + + /* different congestion types match different configurations */ +- switch (hr_dev->caps.cong_type) { ++ switch (hr_qp->cong_type) { + case CONG_TYPE_DCQCN: + cong_alg->alg_sel = CONG_DCQCN; + cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; +@@ -4771,8 +4774,8 @@ static int check_cong_type(struct ib_qp *ibqp, + default: + ibdev_warn(&hr_dev->ib_dev, + "invalid type(%u) for congestion selection.\n", +- hr_dev->caps.cong_type); +- hr_dev->caps.cong_type = CONG_TYPE_DCQCN; ++ hr_qp->cong_type); ++ hr_qp->cong_type = CONG_TYPE_DCQCN; + cong_alg->alg_sel = CONG_DCQCN; + cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; + cong_alg->dip_vld = DIP_INVALID; +@@ -4791,6 +4794,7 @@ static int fill_cong_field(struct ib_qp *ibqp, const struct ib_qp_attr *attr, + struct hns_roce_congestion_algorithm cong_field; + struct ib_device *ibdev = ibqp->device; + struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); ++ struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); + u32 dip_idx = 0; + int ret; + +@@ -4803,7 +4807,7 @@ static int fill_cong_field(struct ib_qp *ibqp, const struct ib_qp_attr *attr, + return ret; + + hr_reg_write(context, QPC_CONG_ALGO_TMPL_ID, hr_dev->cong_algo_tmpl_id + +- hr_dev->caps.cong_type * HNS_ROCE_CONG_SIZE); ++ hr_qp->cong_type * HNS_ROCE_CONG_SIZE); + hr_reg_clear(qpc_mask, QPC_CONG_ALGO_TMPL_ID); + hr_reg_write(&context->ext, QPCEX_CONG_ALG_SEL, cong_field.alg_sel); + hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SEL); +-- +2.39.1.1.gbe015eda0162 + diff --git a/series.conf b/series.conf index cc396f7..2eac14e 100644 --- a/series.conf +++ b/series.conf @@ -45682,6 +45682,7 @@ patches.suse/nilfs2-prevent-kernel-bug-at-submit_bh_wbc.patch patches.suse/RDMA-irdma-Remove-duplicate-assignment.patch patches.suse/RDMA-srpt-Do-not-register-event-handler-until-srpt-d.patch + patches.suse/RDMA-hns-Fix-mis-modifying-default-congestion-contro.patch # jejb/scsi for-next patches.suse/scsi-lpfc-Initialize-status-local-variable-in-lpfc_s.patch