From: Hersen Wu <hersenxs.wu@amd.com>
Date: Fri, 23 Dec 2016 15:13:13 -0500
Subject: drm/amd/display: set HBR3 and TPS4 capable flags
Git-commit: 5a7a1eebc6199a8e19cc6497cffb3e16d9d55333
Patch-mainline: v4.15-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166

Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Zeyu Fan <Zeyu.Fan@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c |   10 ++++++++++
 1 file changed, 10 insertions(+)

--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
@@ -1068,9 +1068,19 @@ bool dce110_link_encoder_construct(
 			&bp_cap_info))
 		enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
 				bp_cap_info.DP_HBR2_CAP;
+		enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
+				bp_cap_info.DP_HBR3_EN;
+
 	}
+
+	/* TODO: check PPLIB maxPhyClockInKHz <= 540000, if yes,
+	 * IS_HBR3_CAPABLE = 0.
+	 */
+
 	/* test pattern 3 support */
 	enc110->base.features.flags.bits.IS_TPS3_CAPABLE = true;
+	/* test pattern 4 support */
+	enc110->base.features.flags.bits.IS_TPS4_CAPABLE = true;
 
 	enc110->base.features.flags.bits.IS_Y_ONLY_CAPABLE = false;
 	/*