From: Thierry Reding Date: Wed, 30 Aug 2017 17:41:00 +0200 Subject: drm/tegra: dc: Perform a complete reset sequence Git-commit: a2f2f7403e1ea192ce79584d7050c46e455409dd Patch-mainline: v4.15-rc1 References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166 In order for the reset to be applied properly, the module clock must be enabled during the assertion. Signed-off-by: Thierry Reding Acked-by: Petr Tesarik --- drivers/gpu/drm/tegra/dc.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -1997,8 +1997,22 @@ static int tegra_dc_probe(struct platfor return PTR_ERR(dc->rst); } - if (!dc->soc->broken_reset) - reset_control_assert(dc->rst); + /* assert reset and disable clock */ + if (!dc->soc->broken_reset) { + err = clk_prepare_enable(dc->clk); + if (err < 0) + return err; + + usleep_range(2000, 4000); + + err = reset_control_assert(dc->rst); + if (err < 0) + return err; + + usleep_range(2000, 4000); + + clk_disable_unprepare(dc->clk); + } if (dc->soc->has_powergate) { if (dc->pipe == 0)