From: Tony Cheng Date: Tue, 21 Nov 2017 17:51:50 -0500 Subject: drm/amd/display: Set mpcc_disconnect_pending during MPC reset Git-commit: cc55b1f5c31aba89c9b504b7400d0e247e8ce1da Patch-mainline: v4.16-rc1 References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166 This prevents an issue where the MPCC will not go to idle due to us not waiting for it to become idle during disable plane. Signed-off-by: Andrew Jiang Signed-off-by: Tony Cheng Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher Acked-by: Petr Tesarik --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 18 ++++++++++---- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 +-- 2 files changed, 16 insertions(+), 6 deletions(-) --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c @@ -42,15 +42,25 @@ void hubp1_set_blank(struct hubp *hubp, { struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); uint32_t blank_en = blank ? 1 : 0; + uint32_t reg_val = 0; - REG_UPDATE_2(DCHUBP_CNTL, + reg_val = REG_UPDATE_2(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en, HUBP_TTU_DISABLE, blank_en); if (blank) { - REG_WAIT(DCHUBP_CNTL, - HUBP_NO_OUTSTANDING_REQ, 1, - 1, 200); + if (reg_val) { + /* init sequence workaround: in case HUBP is + * power gated, this wait would timeout. + * + * we just wrote reg_val to non-0, if it stay 0 + * it means HUBP is gated + */ + REG_WAIT(DCHUBP_CNTL, + HUBP_NO_OUTSTANDING_REQ, 1, + 1, 200); + } + hubp->mpcc_id = 0xf; hubp->opp_id = 0xf; } --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -782,8 +782,8 @@ static void dcn10_init_hw(struct dc *dc) hubp->opp_id = 0xf; hubp->power_gated = false; - if (hubp->opp_id != 0xf) - pipe_ctx->stream_res.opp = dc->res_pool->opps[hubp->opp_id]; + dc->res_pool->opps[i]->mpcc_disconnect_pending[i] = true; + pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; plane_atomic_disconnect(dc, pipe_ctx); }