From d5fb43cb7fffc8f6863d68456252bcf3f06a070a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Wed, 29 Nov 2017 17:37:31 +0200 Subject: [PATCH] drm/i915: Wait for pipe to start on i830 as well Mime-version: 1.0 Content-type: text/plain; charset=UTF-8 Content-transfer-encoding: 8bit Git-commit: d5fb43cb7fffc8f6863d68456252bcf3f06a070a Patch-mainline: v4.16-rc1 References: FATE#322643 bsc#1055900 We should make sure the pipe has fully started when we enable it from the i830 "power well". Otherwise theoretically i830 could also hit problems with vblank timestamps jumping around (since we skip the wait during modeset on i830). Additionally moving planes between the pipes etc. might not work correctly until both pipes are actually up and running. V2: Less pointless duplication in the code (Chris) Cc: Chris Wilson Reviewed-by: Chris Wilson Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20171129153732.3612-2-ville.syrjala@linux.intel.com Acked-by: Takashi Iwai --- drivers/gpu/drm/i915/intel_display.c | 3 +++ 1 file changed, 3 insertions(+) --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -14725,6 +14725,7 @@ int intel_modeset_init(struct drm_device void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) { + struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); /* 640x480@60Hz, ~25175 kHz */ struct dpll clock = { .m1 = 18, @@ -14788,6 +14789,8 @@ void i830_enable_pipe(struct drm_i915_pr I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE); POSTING_READ(PIPECONF(pipe)); + + intel_wait_for_pipe_scanline_moving(crtc); } void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)