From 3d65a735d8341830ef8ec57e290ed785b01085a1 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 6 Apr 2017 16:44:14 +0300 Subject: [PATCH] drm/i915/mst: use max link not sink lane count Mime-version: 1.0 Content-type: text/plain; charset=UTF-8 Content-transfer-encoding: 8bit Git-commit: 3d65a735d8341830ef8ec57e290ed785b01085a1 Patch-mainline: v4.13-rc1 References: FATE#322643 bsc#1055900 The source might not support as many lanes as the sink, or the link training might have failed at higher lane counts. Take these into account. Cc: Dhinakaran Pandiyan Cc: Manasi Navare Cc: Ville Syrjälä Reviewed-by: Manasi Navare Signed-off-by: Jani Nikula Link: http://patchwork.freedesktop.org/patch/msgid/cf59530acafaf9258fb643d321ad251b44f34e29.1491485983.git.jani.nikula@intel.com Acked-by: Takashi Iwai --- drivers/gpu/drm/i915/intel_dp.c | 2 +- drivers/gpu/drm/i915/intel_dp_mst.c | 5 +++-- drivers/gpu/drm/i915/intel_drv.h | 1 + 3 files changed, 5 insertions(+), 3 deletions(-) --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -177,7 +177,7 @@ static int intel_dp_max_common_lane_coun return min(source_max, sink_max); } -static int intel_dp_max_lane_count(struct intel_dp *intel_dp) +int intel_dp_max_lane_count(struct intel_dp *intel_dp) { return intel_dp->max_link_lane_count; } --- a/drivers/gpu/drm/i915/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/intel_dp_mst.c @@ -58,7 +58,8 @@ static bool intel_dp_mst_compute_config( * for MST we always configure max link bw - the spec doesn't * seem to suggest we should do otherwise. */ - lane_count = drm_dp_max_lane_count(intel_dp->dpcd); + lane_count = intel_dp_max_lane_count(intel_dp); + pipe_config->lane_count = lane_count; pipe_config->pipe_bpp = bpp; @@ -381,7 +382,7 @@ intel_dp_mst_mode_valid(struct drm_conne int max_rate, mode_rate, max_lanes, max_link_clock; max_link_clock = intel_dp_max_link_rate(intel_dp); - max_lanes = drm_dp_max_lane_count(intel_dp->dpcd); + max_lanes = intel_dp_max_lane_count(intel_dp); max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); mode_rate = intel_dp_link_required(mode->clock, bpp); --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1494,6 +1494,7 @@ void intel_dp_add_properties(struct inte void intel_dp_mst_suspend(struct drm_device *dev); void intel_dp_mst_resume(struct drm_device *dev); int intel_dp_max_link_rate(struct intel_dp *intel_dp); +int intel_dp_max_lane_count(struct intel_dp *intel_dp); int intel_dp_rate_select(struct intel_dp *intel_dp, int rate); void intel_dp_hot_plug(struct intel_encoder *intel_encoder); void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);