diff --git a/patches.kernel.org/6.3.3-217-drm-i915-mtl-Add-workarounds-Wa_14017066071-and.patch b/patches.kernel.org/6.3.3-217-drm-i915-mtl-Add-workarounds-Wa_14017066071-and.patch
new file mode 100644
index 0000000..8676358
--- /dev/null
+++ b/patches.kernel.org/6.3.3-217-drm-i915-mtl-Add-workarounds-Wa_14017066071-and.patch
@@ -0,0 +1,64 @@
+From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
+Date: Wed, 29 Mar 2023 18:23:35 -0300
+Subject: [PATCH] drm/i915/mtl: Add workarounds Wa_14017066071 and
+ Wa_14017654203
+References: bsc#1012628
+Patch-mainline: 6.3.3
+Git-commit: 5fba65efa7cfb8cef227a2c555deb10327a5e27b
+
+[ Upstream commit 5fba65efa7cfb8cef227a2c555deb10327a5e27b ]
+
+Both workarounds require the same implementation and apply to MTL P and
+M from stepping A0 to B0 (exclusive).
+
+v2:
+  - Remove unrelated brace removal. (Matt)
+
+Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
+Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
+Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
+Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20230329212336.106161-2-gustavo.sousa@intel.com
+Stable-dep-of: 81900e3a3775 ("drm/i915: disable sampler indirect state in bindless heap")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+Signed-off-by: Jiri Slaby <jslaby@suse.cz>
+---
+ drivers/gpu/drm/i915/gt/intel_gt_regs.h     | 1 +
+ drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +++++++++
+ 2 files changed, 10 insertions(+)
+
+diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+index be0f6e30..15b86368 100644
+--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
++++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+@@ -1145,6 +1145,7 @@
+ #define   ENABLE_SMALLPL			REG_BIT(15)
+ #define   SC_DISABLE_POWER_OPTIMIZATION_EBB	REG_BIT(9)
+ #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG	REG_BIT(5)
++#define   MTL_DISABLE_SAMPLER_SC_OOO		REG_BIT(3)
+ 
+ #define GEN9_HALF_SLICE_CHICKEN7		MCR_REG(0xe194)
+ #define   DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA	REG_BIT(15)
+diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
+index 485c5cc5..bfdffb6a 100644
+--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
++++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
+@@ -3015,6 +3015,15 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
+ 
+ 	add_render_compute_tuning_settings(i915, wal);
+ 
++	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
++	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
++		/*
++		 * Wa_14017066071
++		 * Wa_14017654203
++		 */
++		wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
++				 MTL_DISABLE_SAMPLER_SC_OOO);
++
+ 	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+ 	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
+ 	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
+-- 
+2.35.3
+
diff --git a/series.conf b/series.conf
index 4c679e5..cd0bff5 100644
--- a/series.conf
+++ b/series.conf
@@ -950,6 +950,7 @@
 	patches.kernel.org/6.3.3-214-drm-amd-display-merge-dc_link.h-into-dc.h-and-d.patch
 	patches.kernel.org/6.3.3-215-drm-amd-display-hpd-rx-irq-not-working-with-eDP.patch
 	patches.kernel.org/6.3.3-216-drm-i915-Add-_PICK_EVEN_2RANGES.patch
+	patches.kernel.org/6.3.3-217-drm-i915-mtl-Add-workarounds-Wa_14017066071-and.patch
 
 	########################################################
 	# Build fixes that apply to the vanilla kernel too.