From: Dmytro Laktyushkin Date: Fri, 28 Jul 2017 08:16:27 -0400 Subject: drm/amd/display: Fixed mpc add, enable always scaler for video surface. Git-commit: b823defeb73aa8737006abe73844fd697ecf6983 Patch-mainline: v4.15-rc1 References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166 Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher Acked-by: Petr Tesarik --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 6 +++--- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 4 ++++ 2 files changed, 7 insertions(+), 3 deletions(-) --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c @@ -229,9 +229,9 @@ static void mpc10_mpcc_add(struct mpc *m mpc10_set_bg_color(mpc10, &cfg->black_color, mpcc_id); mpc10->mpcc_in_use_mask |= 1 << mpcc_id; - for (z_idx = cfg->z_index; z_idx < cfg->opp->mpc_tree.num_pipes; z_idx++) { - cfg->opp->mpc_tree.dpp[z_idx + 1] = cfg->opp->mpc_tree.dpp[z_idx]; - cfg->opp->mpc_tree.mpcc[z_idx + 1] = cfg->opp->mpc_tree.mpcc[z_idx]; + for (z_idx = cfg->opp->mpc_tree.num_pipes; z_idx > cfg->z_index; z_idx--) { + cfg->opp->mpc_tree.dpp[z_idx] = cfg->opp->mpc_tree.dpp[z_idx - 1]; + cfg->opp->mpc_tree.mpcc[z_idx] = cfg->opp->mpc_tree.mpcc[z_idx - 1]; } cfg->opp->mpc_tree.dpp[cfg->z_index] = cfg->mi->inst; cfg->opp->mpc_tree.mpcc[cfg->z_index] = mpcc_id; --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -422,6 +422,10 @@ static const struct dc_debug debug_defau .force_abm_enable = false, .timing_trace = false, .clock_trace = true, + /* spread sheet doesn't handle taps_c is one properly, + * need to enable scaler for video surface to pass + * bandwidth validation.*/ + .always_scale = true, .disable_pplib_clock_request = true, .disable_pplib_wm_range = false, #if defined(CONFIG_DRM_AMD_DC_DCN1_0)