From: Rex Zhu Date: Tue, 23 Jan 2018 17:31:17 +0800 Subject: drm/amd/pp: Delete unnecessary function argument Git-commit: c1f2fb6b6371980dfdaea1ceba7269ccac6fda3f Patch-mainline: v4.17-rc1 References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166 in populate_single_graphic_level for smu7 Reviewed-by: Alex Deucher Signed-off-by: Rex Zhu Signed-off-by: Alex Deucher Acked-by: Petr Tesarik --- drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c | 6 ++---- drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 6 ++---- drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c | 4 +--- drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c | 6 ++---- drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c | 4 +--- 5 files changed, 8 insertions(+), 18 deletions(-) --- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c @@ -411,8 +411,7 @@ static uint8_t ci_get_sleep_divider_id_f } static int ci_populate_single_graphic_level(struct pp_hwmgr *hwmgr, - uint32_t clock, uint16_t sclk_al_threshold, - struct SMU7_Discrete_GraphicsLevel *level) + uint32_t clock, struct SMU7_Discrete_GraphicsLevel *level) { int result; struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); @@ -438,7 +437,7 @@ static int ci_populate_single_graphic_le clock, &level->MinVddcPhases); - level->ActivityLevel = sclk_al_threshold; + level->ActivityLevel = data->current_profile_setting.sclk_activity; level->CcPwrDynRm = 0; level->CcPwrDynRm1 = 0; level->EnabledForActivity = 0; @@ -492,7 +491,6 @@ static int ci_populate_all_graphic_level for (i = 0; i < dpm_table->sclk_table.count; i++) { result = ci_populate_single_graphic_level(hwmgr, dpm_table->sclk_table.dpm_levels[i].value, - data->current_profile_setting.sclk_activity, &levels[i]); if (result) return result; --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c @@ -968,8 +968,7 @@ static int fiji_calculate_sclk_params(st } static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr, - uint32_t clock, uint16_t sclk_al_threshold, - struct SMU73_Discrete_GraphicsLevel *level) + uint32_t clock, struct SMU73_Discrete_GraphicsLevel *level) { int result; /* PP_Clocks minClocks; */ @@ -996,7 +995,7 @@ static int fiji_populate_single_graphic_ return result); level->SclkFrequency = clock; - level->ActivityLevel = sclk_al_threshold; + level->ActivityLevel = data->current_profile_setting.sclk_activity; level->CcPwrDynRm = 0; level->CcPwrDynRm1 = 0; level->EnabledForActivity = 0; @@ -1059,7 +1058,6 @@ static int fiji_populate_all_graphic_lev for (i = 0; i < dpm_table->sclk_table.count; i++) { result = fiji_populate_single_graphic_level(hwmgr, dpm_table->sclk_table.dpm_levels[i].value, - data->current_profile_setting.sclk_activity, &levels[i]); if (result) return result; --- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c @@ -894,7 +894,6 @@ static int iceland_populate_phase_value_ static int iceland_populate_single_graphic_level(struct pp_hwmgr *hwmgr, uint32_t engine_clock, - uint16_t sclk_activity_level_threshold, SMU71_Discrete_GraphicsLevel *graphic_level) { int result; @@ -920,7 +919,7 @@ static int iceland_populate_single_graph &graphic_level->MinVddcPhases); /* Indicates maximum activity level for this performance level. 50% for now*/ - graphic_level->ActivityLevel = sclk_activity_level_threshold; + graphic_level->ActivityLevel = data->current_profile_setting.sclk_activity; graphic_level->CcPwrDynRm = 0; graphic_level->CcPwrDynRm1 = 0; @@ -985,7 +984,6 @@ static int iceland_populate_all_graphic_ for (i = 0; i < dpm_table->sclk_table.count; i++) { result = iceland_populate_single_graphic_level(hwmgr, dpm_table->sclk_table.dpm_levels[i].value, - data->current_profile_setting.sclk_activity, &(smu_data->smc_state_table.GraphicsLevel[i])); if (result != 0) return result; --- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c @@ -934,8 +934,7 @@ static int polaris10_calculate_sclk_para } static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr, - uint32_t clock, uint16_t sclk_al_threshold, - struct SMU74_Discrete_GraphicsLevel *level) + uint32_t clock, struct SMU74_Discrete_GraphicsLevel *level) { int result; /* PP_Clocks minClocks; */ @@ -962,7 +961,7 @@ static int polaris10_populate_single_gra "can not find VDDC voltage value for " "VDDC engine clock dependency table", return result); - level->ActivityLevel = sclk_al_threshold; + level->ActivityLevel = data->current_profile_setting.sclk_activity; level->CcPwrDynRm = 0; level->CcPwrDynRm1 = 0; @@ -1033,7 +1032,6 @@ static int polaris10_populate_all_graphi result = polaris10_populate_single_graphic_level(hwmgr, dpm_table->sclk_table.dpm_levels[i].value, - hw_data->current_profile_setting.sclk_activity, &(smu_data->smc_state_table.GraphicsLevel[i])); if (result) return result; --- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c @@ -608,7 +608,6 @@ static int tonga_calculate_sclk_params(s static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr, uint32_t engine_clock, - uint16_t sclk_activity_level_threshold, SMU72_Discrete_GraphicsLevel *graphic_level) { int result; @@ -636,7 +635,7 @@ static int tonga_populate_single_graphic /* SCLK frequency in units of 10KHz*/ graphic_level->SclkFrequency = engine_clock; /* Indicates maximum activity level for this performance level. 50% for now*/ - graphic_level->ActivityLevel = sclk_activity_level_threshold; + graphic_level->ActivityLevel = data->current_profile_setting.sclk_activity; graphic_level->CcPwrDynRm = 0; graphic_level->CcPwrDynRm1 = 0; @@ -704,7 +703,6 @@ static int tonga_populate_all_graphic_le for (i = 0; i < dpm_table->sclk_table.count; i++) { result = tonga_populate_single_graphic_level(hwmgr, dpm_table->sclk_table.dpm_levels[i].value, - data->current_profile_setting.sclk_activity, &(smu_data->smc_state_table.GraphicsLevel[i])); if (result != 0) return result;