From: Charlene Liu Date: Fri, 3 Mar 2017 13:44:35 -0500 Subject: drm/amd/display: move refclk from dc to resource_pool Git-commit: 5ac3d3c9b79fb607fc25268c8dbd220ac14f5ac6 Patch-mainline: v4.15-rc1 References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166 Signed-off-by: Charlene Liu Acked-by: Harry Wentland Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher Acked-by: Petr Tesarik --- drivers/gpu/drm/amd/display/dc/core/dc.c | 7 ------ drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 25 +++++++++++++++++----- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 2 - drivers/gpu/drm/amd/display/dc/dc_types.h | 1 drivers/gpu/drm/amd/display/dc/inc/core_types.h | 1 5 files changed, 22 insertions(+), 14 deletions(-) --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -467,7 +467,6 @@ static bool construct(struct core_dc *dc else { /* Create BIOS parser */ struct bp_init_data bp_init_data; - struct firmware_info fw_info = { { 0 } }; bp_init_data.ctx = dc_ctx; bp_init_data.bios = init_params->asic_id.atombios_base_address; @@ -481,12 +480,6 @@ static bool construct(struct core_dc *dc } dc_ctx->created_bios = true; - - if (dc_ctx->dc_bios->funcs->get_firmware_info( - dc_ctx->dc_bios, &fw_info) == BP_RESULT_OK) { - dc->ctx->ref_clock_inKhz = fw_info.pll_info.crystal_frequency; - } else - ASSERT_CRITICAL(false); } /* Create I2C AUX */ --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -31,6 +31,7 @@ #include "opp.h" #include "timing_generator.h" #include "transform.h" +#include "core_types.h" #include "set_mode_types.h" #include "virtual/virtual_stream_encoder.h" @@ -77,25 +78,39 @@ struct resource_pool *dc_create_resource enum dce_version dc_version, struct hw_asic_id asic_id) { + struct resource_pool *res_pool = NULL; switch (dc_version) { case DCE_VERSION_8_0: - return dce80_create_resource_pool( + res_pool = dce80_create_resource_pool( num_virtual_links, dc); + break; case DCE_VERSION_10_0: - return dce100_create_resource_pool( + res_pool = dce100_create_resource_pool( num_virtual_links, dc); + break; case DCE_VERSION_11_0: - return dce110_create_resource_pool( + res_pool = dce110_create_resource_pool( num_virtual_links, dc, asic_id); + break; case DCE_VERSION_11_2: - return dce112_create_resource_pool( + res_pool = dce112_create_resource_pool( num_virtual_links, dc); + break; default: break; } + if (res_pool != NULL) { + struct firmware_info fw_info = { { 0 } }; + + if (dc->ctx->dc_bios->funcs->get_firmware_info( + dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) { + res_pool->ref_clock_inKhz = fw_info.pll_info.crystal_frequency; + } else + ASSERT_CRITICAL(false); + } - return false; + return res_pool; } void dc_destroy_resource_pool(struct core_dc *dc) --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -237,7 +237,7 @@ bool dc_stream_set_cursor_position( struct input_pixel_processor *ipp = pipe_ctx->ipp; struct dc_cursor_mi_param param = { .pixel_clk_khz = dc_stream->timing.pix_clk_khz, - .ref_clk_khz = core_dc->ctx->ref_clock_inKhz, + .ref_clk_khz = res_ctx->pool->ref_clock_inKhz, .viewport_x_start = pipe_ctx->scl_data.viewport.x, .viewport_width = pipe_ctx->scl_data.viewport.width, .h_scale_ratio = pipe_ctx->scl_data.ratios.horz, --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -91,7 +91,6 @@ struct dc_context { bool created_bios; struct gpio_service *gpio_service; struct i2caux *i2caux; - unsigned int ref_clock_inKhz; }; --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -239,6 +239,7 @@ struct resource_pool { unsigned int pipe_count; unsigned int underlay_pipe_index; unsigned int stream_enc_count; + unsigned int ref_clock_inKhz; /* * reserved clock source for DP