From: Corbin McElhanney Date: Thu, 3 Aug 2017 14:20:14 -0400 Subject: drm/amd/display: Add more pstate sanity checks Git-commit: 665da60f23d8c6bda5431529a73be49b3b9d97cb Patch-mainline: v4.15-rc1 References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166 Signed-off-by: Corbin McElhanney Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher Acked-by: Petr Tesarik --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 24 ++++++++++++++ 1 file changed, 24 insertions(+) --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1767,6 +1767,10 @@ static void dcn10_power_on_fe( struct dc_plane_state *plane_state = pipe_ctx->plane_state; struct dce_hwseq *hws = dc->hwseq; + if (dc->public.debug.sanity_checks) { + verify_allow_pstate_change_high(dc->hwseq); + } + power_on_plane(dc->hwseq, pipe_ctx->pipe_idx); @@ -1813,6 +1817,10 @@ static void dcn10_power_on_fe( pipe_ctx->plane_res.scl_data.recout.y); print_rq_dlg_ttu(dc, pipe_ctx); } + + if (dc->public.debug.sanity_checks) { + verify_allow_pstate_change_high(dc->hwseq); + } } static void program_gamut_remap(struct pipe_ctx *pipe_ctx) @@ -2287,6 +2295,10 @@ static void dcn10_set_bandwidth( { struct dm_pp_clock_for_voltage_req clock; + if (dc->public.debug.sanity_checks) { + verify_allow_pstate_change_high(dc->hwseq); + } + if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) return; @@ -2338,6 +2350,10 @@ static void dcn10_set_bandwidth( } dcn10_pplib_apply_display_requirements(dc, context); + if (dc->public.debug.sanity_checks) { + verify_allow_pstate_change_high(dc->hwseq); + } + /* need to fix this function. not doing the right thing here */ } @@ -2459,6 +2475,10 @@ static void dcn10_wait_for_mpcc_disconne { int i; + if (dc->public.debug.sanity_checks) { + verify_allow_pstate_change_high(dc->hwseq); + } + if (!pipe_ctx->stream_res.opp) return; @@ -2473,6 +2493,10 @@ static void dcn10_wait_for_mpcc_disconne } } + if (dc->public.debug.sanity_checks) { + verify_allow_pstate_change_high(dc->hwseq); + } + } static bool dcn10_dummy_display_power_gating(