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From 282f75e33f93e46854345598f576d052d5cfe390 Mon Sep 17 00:00:00 2001
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From: Fabian Vogt <fvogt@suse.de>
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Date: Thu, 8 Dec 2022 12:50:12 +0100
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Subject: [PATCH] Add x86-64 architecture levels (v2-v4) as architectures
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The x86_64 SysV psABI defines four levels of x86_64 with certain CPU features
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required for each level. Those definitions are meant to be generically useful
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and recognized as such by glibc and gcc as well.
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For backward-compatibility and to avoid surprises, default to building x86_64
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even on v2+ capable machines.
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---
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installplatform | 2 +-
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lib/rpmrc.c | 75 +++++++++++++++++++++++++++++++++++++++++++++++++
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macros.in | 4 +++
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rpmrc.in | 18 ++++++++++++
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4 files changed, 98 insertions(+), 1 deletion(-)
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--- installplatform
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+++ installplatform
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@@ -78,7 +78,7 @@ for ARCH in noarch `grep ^arch_canon $RP
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CANONARCH=i386
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CANONCOLOR=0
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;;
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- x86_64|amd64|ia32e)
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+ x86_64*|amd64|ia32e)
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ISANAME=x86
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ISABITS=64
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CANONARCH=x86_64
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--- lib/rpmrc.c
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+++ lib/rpmrc.c
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@@ -735,6 +735,71 @@ exit:
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return rc;
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}
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+# if defined(__linux__) && defined(__x86_64__)
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+static inline void cpuid(uint32_t op, uint32_t op2, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
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+{
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+ asm volatile (
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+ "cpuid\n"
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+ : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
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+ : "a" (op), "c" (op2));
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+}
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+
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+/* From gcc's gcc/config/i386/cpuid.h */
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+/* Features (%eax == 1) */
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+/* %ecx */
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+#define bit_SSE3 (1 << 0)
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+#define bit_LZCNT (1 << 5)
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+#define bit_SSSE3 (1 << 9)
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+#define bit_FMA (1 << 12)
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+#define bit_CMPXCHG16B (1 << 13)
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+#define bit_SSE4_1 (1 << 19)
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+#define bit_SSE4_2 (1 << 20)
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+#define bit_MOVBE (1 << 22)
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+#define bit_POPCNT (1 << 23)
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+#define bit_OSXSAVE (1 << 27)
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+#define bit_AVX (1 << 28)
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+#define bit_F16C (1 << 29)
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+
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+/* Extended Features (%eax == 0x80000001) */
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+/* %ecx */
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+#define bit_LAHF_LM (1 << 0)
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+
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+/* Extended Features (%eax == 7) */
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+/* %ebx */
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+#define bit_BMI (1 << 3)
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+#define bit_AVX2 (1 << 5)
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+#define bit_BMI2 (1 << 8)
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+#define bit_AVX512F (1 << 16)
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+#define bit_AVX512DQ (1 << 17)
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+#define bit_AVX512CD (1 << 28)
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+#define bit_AVX512BW (1 << 30)
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+#define bit_AVX512VL (1u << 31)
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+
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+static int get_x86_64_level(void)
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+{
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+ int level = 1;
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+
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+ unsigned int op_1_ecx = 0, op_80000001_ecx = 0, op_7_ebx = 0, unused;
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+ cpuid(1, 0, &unused, &unused, &op_1_ecx, &unused);
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+ cpuid(0x80000001, 0, &unused, &unused, &op_80000001_ecx, &unused);
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+ cpuid(7, 0, &unused, &op_7_ebx, &unused, &unused);
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+
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+ const unsigned int op_1_ecx_lv2 = bit_SSE3 | bit_SSSE3 | bit_CMPXCHG16B | bit_SSE4_1 | bit_SSE4_2 | bit_POPCNT;
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+ if ((op_1_ecx & op_1_ecx_lv2) == op_1_ecx_lv2 && (op_80000001_ecx & bit_LAHF_LM))
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+ level = 2;
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+
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+ const unsigned int op_1_ecx_lv3 = bit_LZCNT | bit_FMA | bit_MOVBE | bit_OSXSAVE | bit_AVX | bit_F16C;
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+ const unsigned int op_7_ebx_lv3 = bit_BMI | bit_AVX2 | bit_BMI2;
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+ if (level == 2 && (op_1_ecx & op_1_ecx_lv3) == op_1_ecx_lv3 && (op_7_ebx & op_7_ebx_lv3) == op_7_ebx_lv3)
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+ level = 3;
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+
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+ const unsigned int op_7_ebx_lv4 = bit_AVX512F | bit_AVX512DQ | bit_AVX512CD | bit_AVX512BW | bit_AVX512VL;
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+ if (level == 3 && (op_7_ebx & op_7_ebx_lv4) == op_7_ebx_lv4)
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+ level = 4;
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+
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+ return level;
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+}
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+# endif
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# if defined(__linux__) && defined(__i386__)
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#include <setjmp.h>
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@@ -1287,6 +1352,16 @@ static void defaultMachine(rpmrcCtx ctx,
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}
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# endif
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+# if defined(__linux__) && defined(__x86_64__)
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+ {
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+ int x86_64_level = get_x86_64_level();
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+ if (x86_64_level > 1) {
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+ strcpy(un.machine, "x86_64_vX");
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+ un.machine[8] = '0' + x86_64_level;
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+ }
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+ }
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+#endif
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+
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/* the uname() result goes through the arch_canon table */
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canon = lookupInCanonTable(un.machine,
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ctx->tables[RPM_MACHTABLE_INSTARCH].canons,
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--- macros.in
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+++ macros.in
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@@ -1064,6 +1064,10 @@ package or when debugging this package.\
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%ix86 i386 i486 i586 i686 pentium3 pentium4 athlon geode
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#------------------------------------------------------------------------------
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+# arch macro for all supported x86_64 processors
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+%x86_64 x86_64 x86_64_v2 x86_64_v3 x86_64_v4 amd64 em64t
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+
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+#------------------------------------------------------------------------------
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# arch macro for all supported 32-bit ARM processors
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%arm32 armv3l armv4b armv4l armv4tl armv5b armv5l armv5teb armv5tel armv5tejl armv6l armv6hl armv7l armv7hl armv7hnl armv8l armv8hl armv8hnl armv8hcnl
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--- rpmrc.in
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+++ rpmrc.in
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@@ -22,6 +22,10 @@ optflags: athlon -O2 -g -m32 -march=athl
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optflags: geode -Os -g -m32 -march=geode
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optflags: ia64 -O2 -g -fmessage-length=0 -D_FORTIFY_SOURCE=2 -fstack-protector -funwind-tables -fasynchronous-unwind-tables
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optflags: x86_64 -O2 -g -m64 -fmessage-length=0 -D_FORTIFY_SOURCE=2 -fstack-protector -funwind-tables -fasynchronous-unwind-tables
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+optflags: x86_64_v2 -O2 -g -march=x86-64-v2 -m64 -fmessage-length=0 -D_FORTIFY_SOURCE=2 -fstack-protector -funwind-tables -fasynchronous-unwind-tables
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+optflags: x86_64_v3 -O2 -g -march=x86-64-v3 -m64 -fmessage-length=0 -D_FORTIFY_SOURCE=2 -fstack-protector -funwind-tables -fasynchronous-unwind-tables
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+optflags: x86_64_v4 -O2 -g -march=x86-64-v4 -m64 -fmessage-length=0 -D_FORTIFY_SOURCE=2 -fstack-protector -funwind-tables -fasynchronous-unwind-tables
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+
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optflags: amd64 -O2 -g
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optflags: ia32e -O2 -g
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@@ -148,6 +152,9 @@ archcolor: s390x 2
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archcolor: ia64 2
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archcolor: x86_64 2
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+archcolor: x86_64_v2 2
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+archcolor: x86_64_v3 2
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+archcolor: x86_64_v4 2
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archcolor: sh3 1
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archcolor: sh4 1
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@@ -168,6 +175,9 @@ arch_canon: i586: i586 1
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arch_canon: i486: i486 1
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arch_canon: i386: i386 1
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arch_canon: x86_64: x86_64 1
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+arch_canon: x86_64_v2: x86_64_v2 1
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+arch_canon: x86_64_v3: x86_64_v3 1
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+arch_canon: x86_64_v4: x86_64_v4 1
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arch_canon: amd64: amd64 1
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arch_canon: ia32e: ia32e 1
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arch_canon: em64t: em64t 1
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@@ -378,6 +388,9 @@ buildarchtranslate: s390x: s390x
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buildarchtranslate: ia64: ia64
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buildarchtranslate: x86_64: x86_64
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+buildarchtranslate: x86_64_v2: x86_64
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+buildarchtranslate: x86_64_v3: x86_64
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+buildarchtranslate: x86_64_v4: x86_64
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buildarchtranslate: amd64: x86_64
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buildarchtranslate: ia32e: x86_64
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@@ -504,6 +517,9 @@ arch_compat: ia64: i686 noarch
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arch_compat: x86_64: amd64 em64t athlon noarch
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arch_compat: amd64: x86_64 em64t athlon noarch
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arch_compat: ia32e: x86_64 em64t athlon noarch
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+arch_compat: x86_64_v2: x86_64 amd64 em64t athlon noarch
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+arch_compat: x86_64_v3: x86_64_v2 x86_64 amd64 em64t athlon noarch
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+arch_compat: x86_64_v4: x86_64_v3 x86_64_v2 x86_64 amd64 em64t athlon noarch
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arch_compat: sh3: noarch
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arch_compat: sh4: noarch
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@@ -640,6 +656,9 @@ buildarch_compat: s390x: noarch
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buildarch_compat: ia64: noarch
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+buildarch_compat: x86_64_v4: x86_64_v3
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+buildarch_compat: x86_64_v3: x86_64_v2
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+buildarch_compat: x86_64_v2: x86_64
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buildarch_compat: x86_64: noarch
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buildarch_compat: amd64: x86_64
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buildarch_compat: ia32e: x86_64
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