From: Evan Quan <evan.quan@amd.com>
Date: Fri, 20 Oct 2017 15:42:34 +0800
Subject: drm/amd/powerplay: retrieve the real-time coreClock values
Git-commit: 0722382dcc4fd4e53c12db2c2eda9c5c9c903432
Patch-mainline: v4.15-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166
- Currently, the coreClock value for min/max performance level on raven
is hard-coded. Use the real-time value retrieved by GetGfxMinFreqLimit
and GetGfxMaxFreqLimit PPSMC messages
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 28 +++++--------------------
1 file changed, 6 insertions(+), 22 deletions(-)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
@@ -672,36 +672,20 @@ static int rv_get_performance_level(stru
PHM_PerformanceLevelDesignation designation, uint32_t index,
PHM_PerformanceLevel *level)
{
- const struct rv_power_state *ps;
struct rv_hwmgr *data;
- uint32_t level_index;
- uint32_t i;
- uint32_t vol_dep_record_index = 0;
if (level == NULL || hwmgr == NULL || state == NULL)
return -EINVAL;
data = (struct rv_hwmgr *)(hwmgr->backend);
- ps = cast_const_rv_ps(state);
- level_index = index > ps->level - 1 ? ps->level - 1 : index;
- level->coreClock = 30000;
-
- if (designation == PHM_PerformanceLevelDesignation_PowerContainment) {
- for (i = 1; i < ps->level; i++) {
- if (ps->levels[i].engine_clock > data->dce_slow_sclk_threshold) {
- level->coreClock = 30000;
- break;
- }
- }
- }
-
- if (level_index == 0) {
- vol_dep_record_index = data->clock_vol_info.vdd_dep_on_fclk->count - 1;
- level->memory_clock =
- data->clock_vol_info.vdd_dep_on_fclk->entries[vol_dep_record_index].clk;
- } else {
+ if (index == 0) {
level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk;
+ level->coreClock = data->gfx_min_freq_limit;
+ } else {
+ level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[
+ data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk;
+ level->coreClock = data->gfx_max_freq_limit;
}
level->nonLocalMemoryFreq = 0;