From: Rex Zhu <Rex.Zhu@amd.com>
Date: Wed, 21 Mar 2018 16:19:21 +0800
Subject: drm/amd/pp: Add smu irq handlers for legacy asics
Git-commit: 031ec948a8dd12c4848b045fe8a64db22b91684c
Patch-mainline: v4.17-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 27 +++++++++++++++++++++++
1 file changed, 27 insertions(+)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3998,8 +3998,35 @@ static int smu7_set_max_fan_rpm_output(s
PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
}
+static const struct amdgpu_irq_src_funcs smu7_irq_funcs = {
+ .process = phm_irq_process,
+};
+
static int smu7_register_irq_handlers(struct pp_hwmgr *hwmgr)
{
+ struct amdgpu_irq_src *source =
+ kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
+
+ if (!source)
+ return -ENOMEM;
+
+ source->funcs = &smu7_irq_funcs;
+
+ amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
+ AMDGPU_IH_CLIENTID_LEGACY,
+ 230,
+ source);
+ amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
+ AMDGPU_IH_CLIENTID_LEGACY,
+ 231,
+ source);
+
+ /* Register CTF(GPIO_19) interrupt */
+ amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
+ AMDGPU_IH_CLIENTID_LEGACY,
+ 83,
+ source);
+
return 0;
}