From 751a93a15cde277ada4e1be14d93eb13a0dc3edd Mon Sep 17 00:00:00 2001
From: Matt Roper <matthew.d.roper@intel.com>
Date: Tue, 10 Sep 2019 08:42:49 -0700
Subject: drm/i915: Consolidate {bxt,cnl,icl}_uninit_cdclk
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Git-commit: 751a93a15cde277ada4e1be14d93eb13a0dc3edd
Patch-mainline: v5.5-rc1
References: bsc#1152489
The uninitialize flow is the same on all of these platforms, aside from
calculating a different frequency level.
v2: Reverse platform conditional order for consistency. (Ville)
Cc: Ville Syrj채l채 <ville.syrjala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ville Syrj채l채 <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190910154252.30503-6-matthew.d.roper@intel.com
Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 48 +++++++---------------
1 file changed, 14 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index ebed87a64c98..679aeebfbca5 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1683,7 +1683,18 @@ static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
cdclk_state.cdclk = cdclk_state.bypass;
cdclk_state.vco = 0;
- cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
+ if (IS_ELKHARTLAKE(dev_priv))
+ cdclk_state.voltage_level =
+ ehl_calc_voltage_level(cdclk_state.cdclk);
+ else if (INTEL_GEN(dev_priv) >= 11)
+ cdclk_state.voltage_level =
+ icl_calc_voltage_level(cdclk_state.cdclk);
+ else if (INTEL_GEN(dev_priv) >= 10)
+ cdclk_state.voltage_level =
+ cnl_calc_voltage_level(cdclk_state.cdclk);
+ else
+ cdclk_state.voltage_level =
+ bxt_calc_voltage_level(cdclk_state.cdclk);
bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
}
@@ -1729,22 +1740,6 @@ static void icl_init_cdclk(struct drm_i915_private *dev_priv)
bxt_set_cdclk(dev_priv, &sanitized_state, INVALID_PIPE);
}
-static void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
-{
- struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
-
- cdclk_state.cdclk = cdclk_state.bypass;
- cdclk_state.vco = 0;
- if (IS_ELKHARTLAKE(dev_priv))
- cdclk_state.voltage_level =
- ehl_calc_voltage_level(cdclk_state.cdclk);
- else
- cdclk_state.voltage_level =
- icl_calc_voltage_level(cdclk_state.cdclk);
-
- bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
-}
-
static void cnl_init_cdclk(struct drm_i915_private *dev_priv)
{
struct intel_cdclk_state cdclk_state;
@@ -1764,17 +1759,6 @@ static void cnl_init_cdclk(struct drm_i915_private *dev_priv)
bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
}
-static void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
-{
- struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
-
- cdclk_state.cdclk = cdclk_state.bypass;
- cdclk_state.vco = 0;
- cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
-
- bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
-}
-
/**
* intel_cdclk_init - Initialize CDCLK
* @i915: i915 device
@@ -1805,14 +1789,10 @@ void intel_cdclk_init(struct drm_i915_private *i915)
*/
void intel_cdclk_uninit(struct drm_i915_private *i915)
{
- if (INTEL_GEN(i915) >= 11)
- icl_uninit_cdclk(i915);
- else if (IS_CANNONLAKE(i915))
- cnl_uninit_cdclk(i915);
+ if (INTEL_GEN(i915) >= 10 || IS_GEN9_LP(i915))
+ bxt_uninit_cdclk(i915);
else if (IS_GEN9_BC(i915))
skl_uninit_cdclk(i915);
- else if (IS_GEN9_LP(i915))
- bxt_uninit_cdclk(i915);
}
/**
--
2.28.0