From b7629e2f13d727094ca3d4c94b0bea4946ee39d9 Mon Sep 17 00:00:00 2001
From: Likun Gao <Likun.Gao@amd.com>
Date: Wed, 20 Nov 2019 16:21:22 +0800
Subject: drm/amdgpu/mes: correct register offset for sienna_cichlid
Git-commit: 25fc05648f49e083e3cf031626b8ecf86fca5dd1
Patch-mainline: v5.9-rc1
References: jsc#SLE-12680, jsc#SLE-12880, jsc#SLE-12882, jsc#SLE-12883, jsc#SLE-13496, jsc#SLE-15322
Correct CP_MES_IC_OP_CNTL register address for sienna_cichlid on mes v10.1.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Patrik Jakobsson <pjakobsson@suse.de>
---
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 39 +++++++++++++++++++++++---
1 file changed, 35 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
index 8d2469fe2174..447bee159089 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
@@ -31,6 +31,9 @@
#include "v10_structs.h"
#include "mes_api_def.h"
+#define mmCP_MES_IC_OP_CNTL_Sienna_Cichlid 0x2820
+#define mmCP_MES_IC_OP_CNTL_Sienna_Cichlid_BASE_IDX 1
+
MODULE_FIRMWARE("amdgpu/navi10_mes.bin");
MODULE_FIRMWARE("amdgpu/sienna_cichlid_mes.bin");
@@ -490,15 +493,43 @@ static int mes_v10_1_load_microcode(struct amdgpu_device *adev)
WREG32_SOC15(GC, 0, mmCP_MES_MDBOUND_LO, 0x3FFFF);
/* invalidate ICACHE */
- data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL);
+ switch (adev->asic_type) {
+ case CHIP_SIENNA_CICHLID:
+ data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL_Sienna_Cichlid);
+ break;
+ default:
+ data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL);
+ break;
+ }
data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0);
data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);
- WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL, data);
+ switch (adev->asic_type) {
+ case CHIP_SIENNA_CICHLID:
+ WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL_Sienna_Cichlid, data);
+ break;
+ default:
+ WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL, data);
+ break;
+ }
/* prime the ICACHE. */
- data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL);
+ switch (adev->asic_type) {
+ case CHIP_SIENNA_CICHLID:
+ data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL_Sienna_Cichlid);
+ break;
+ default:
+ data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL);
+ break;
+ }
data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1);
- WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL, data);
+ switch (adev->asic_type) {
+ case CHIP_SIENNA_CICHLID:
+ WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL_Sienna_Cichlid, data);
+ break;
+ default:
+ WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL, data);
+ break;
+ }
nv_grbm_select(adev, 0, 0, 0, 0);
mutex_unlock(&adev->srbm_mutex);
--
2.29.2