From 28d59f28562bf3eeedd3689647a4feae1a93f19b Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 15 Jan 2020 06:34:21 +1000
Subject: drm/nouveau/sec2: move interrupt handler to hw-specific module
Git-commit: c9af47bcbde4d3eef3e68c69a29c580e0301a416
Patch-mainline: v5.6-rc1
References: jsc#SLE-12680, jsc#SLE-12880, jsc#SLE-12882, jsc#SLE-12883, jsc#SLE-13496, jsc#SLE-15322
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Patrik Jakobsson <pjakobsson@suse.de>
---
.../gpu/drm/nouveau/nvkm/engine/sec2/base.c | 28 +++++--------------
.../gpu/drm/nouveau/nvkm/engine/sec2/gp102.c | 20 +++++++++++++
.../gpu/drm/nouveau/nvkm/engine/sec2/priv.h | 3 ++
.../gpu/drm/nouveau/nvkm/engine/sec2/tu102.c | 1 +
4 files changed, 31 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c
index f4cf682786c9..bb79488f414d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c
@@ -25,27 +25,6 @@
#include <core/msgqueue.h>
#include <subdev/top.h>
-static void
-nvkm_sec2_intr(struct nvkm_engine *engine)
-{
- struct nvkm_sec2 *sec2 = nvkm_sec2(engine);
- struct nvkm_subdev *subdev = &sec2->engine.subdev;
- struct nvkm_falcon *falcon = &sec2->falcon;
- u32 disp = nvkm_falcon_rd32(falcon, 0x01c);
- u32 intr = nvkm_falcon_rd32(falcon, 0x008) & disp & ~(disp >> 16);
-
- if (intr & 0x00000040) {
- schedule_work(&sec2->work);
- nvkm_falcon_wr32(falcon, 0x004, 0x00000040);
- intr &= ~0x00000040;
- }
-
- if (intr) {
- nvkm_error(subdev, "unhandled intr %08x\n", intr);
- nvkm_falcon_wr32(falcon, 0x004, intr);
- }
-}
-
static void
nvkm_sec2_recv(struct work_struct *work)
{
@@ -60,6 +39,13 @@ nvkm_sec2_recv(struct work_struct *work)
nvkm_msgqueue_recv(sec2->queue);
}
+static void
+nvkm_sec2_intr(struct nvkm_engine *engine)
+{
+ struct nvkm_sec2 *sec2 = nvkm_sec2(engine);
+ sec2->func->intr(sec2);
+}
+
static int
nvkm_sec2_fini(struct nvkm_engine *engine, bool suspend)
{
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c
index 75407cb8a88a..c6919f2886de 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c
@@ -26,6 +26,25 @@ static const struct nvkm_acr_lsf_func
gp102_sec2_acr_0 = {
};
+void
+gp102_sec2_intr(struct nvkm_sec2 *sec2)
+{
+ struct nvkm_subdev *subdev = &sec2->engine.subdev;
+ struct nvkm_falcon *falcon = &sec2->falcon;
+ u32 disp = nvkm_falcon_rd32(falcon, 0x01c);
+ u32 intr = nvkm_falcon_rd32(falcon, 0x008) & disp & ~(disp >> 16);
+
+ if (intr & 0x00000040) {
+ schedule_work(&sec2->work);
+ nvkm_falcon_wr32(falcon, 0x004, 0x00000040);
+ intr &= ~0x00000040;
+ }
+
+ if (intr) {
+ nvkm_error(subdev, "unhandled intr %08x\n", intr);
+ nvkm_falcon_wr32(falcon, 0x004, intr);
+ }
+}
static const struct nvkm_falcon_func
gp102_sec2_flcn = {
@@ -44,6 +63,7 @@ gp102_sec2_flcn = {
const struct nvkm_sec2_func
gp102_sec2 = {
.flcn = &gp102_sec2_flcn,
+ .intr = gp102_sec2_intr,
};
MODULE_FIRMWARE("nvidia/gp102/sec2/desc.bin");
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h
index 6e28b969573b..e5ba6df3d500 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h
@@ -5,8 +5,11 @@
struct nvkm_sec2_func {
const struct nvkm_falcon_func *flcn;
+ void (*intr)(struct nvkm_sec2 *);
};
+void gp102_sec2_intr(struct nvkm_sec2 *);
+
struct nvkm_sec2_fwif {
int version;
int (*load)(struct nvkm_sec2 *, int ver, const struct nvkm_sec2_fwif *);
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/tu102.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/tu102.c
index 5192b3a1e40c..e3eb08f4e9a1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/tu102.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/tu102.c
@@ -38,6 +38,7 @@ tu102_sec2_flcn = {
static const struct nvkm_sec2_func
tu102_sec2 = {
.flcn = &tu102_sec2_flcn,
+ .intr = gp102_sec2_intr,
};
static int
--
2.28.0