From 900872d845d8e691a81afc83ade17135565718d2 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 15 Jan 2020 06:34:21 +1000
Subject: drm/nouveau/flcn: specify queue register offsets from subdev
Git-commit: b826f48a1c127396df2b5e4889994fed6ef3c4a7
Patch-mainline: v5.6-rc1
References: jsc#SLE-12680, jsc#SLE-12880, jsc#SLE-12882, jsc#SLE-12883, jsc#SLE-13496, jsc#SLE-15322
Also fixes the values for Turing, even though we don't use it yet.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Patrik Jakobsson <pjakobsson@suse.de>
---
.../drm/nouveau/include/nvkm/engine/falcon.h | 6 ++++++
.../gpu/drm/nouveau/nvkm/engine/sec2/gp102.c | 2 ++
.../gpu/drm/nouveau/nvkm/engine/sec2/tu102.c | 2 ++
.../gpu/drm/nouveau/nvkm/falcon/msgqueue.c | 19 +------------------
.../nouveau/nvkm/falcon/msgqueue_0137c63d.c | 11 +++++++----
.../nouveau/nvkm/falcon/msgqueue_0148cdec.c | 13 +++++++++----
.../gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c | 2 ++
7 files changed, 29 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h
index fbb57e114c72..46b2424e30f0 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h
@@ -93,6 +93,12 @@ struct nvkm_falcon_func {
int (*enable)(struct nvkm_falcon *falcon);
void (*disable)(struct nvkm_falcon *falcon);
+ struct {
+ u32 head;
+ u32 tail;
+ u32 stride;
+ } cmdq, msgq;
+
struct nvkm_sclass sclass[];
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c
index bb95a2d72b89..0f6e8d002eea 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c
@@ -101,6 +101,8 @@ gp102_sec2_flcn = {
.start = nvkm_falcon_v1_start,
.enable = nvkm_falcon_v1_enable,
.disable = nvkm_falcon_v1_disable,
+ .cmdq = { 0xa00, 0xa04, 8 },
+ .msgq = { 0xa30, 0xa34, 8 },
};
const struct nvkm_sec2_func
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/tu102.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/tu102.c
index c35752765ced..fe9993526f16 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/tu102.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/tu102.c
@@ -36,6 +36,8 @@ tu102_sec2_flcn = {
.start = nvkm_falcon_v1_start,
.enable = nvkm_falcon_v1_enable,
.disable = nvkm_falcon_v1_disable,
+ .cmdq = { 0xc00, 0xc04, 8 },
+ .msgq = { 0xc80, 0xc84, 8 },
};
static const struct nvkm_sec2_func
diff --git a/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c b/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c
index a8bee1e046aa..4d7039d8e498 100644
--- a/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c
+++ b/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c
@@ -384,27 +384,10 @@ msgqueue_handle_init_msg(struct nvkm_msgqueue *priv,
{
struct nvkm_falcon *falcon = priv->falcon;
const struct nvkm_subdev *subdev = falcon->owner;
+ const u32 tail_reg = falcon->func->msgq.tail;
u32 tail;
- u32 tail_reg;
int ret;
- /*
- * Of course the message queue registers vary depending on the falcon
- * used...
- */
- switch (falcon->owner->index) {
- case NVKM_SUBDEV_PMU:
- tail_reg = 0x4cc;
- break;
- case NVKM_ENGINE_SEC2:
- tail_reg = 0xa34;
- break;
- default:
- nvkm_error(subdev, "falcon %s unsupported for msgqueue!\n",
- nvkm_subdev_name[falcon->owner->index]);
- return -EINVAL;
- }
-
/*
* Read the message - queues are not initialized yet so we cannot rely
* on msg_queue_read()
diff --git a/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c b/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c
index fec0273158f6..68de203d80a8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c
+++ b/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c
@@ -136,6 +136,7 @@ init_callback(struct nvkm_msgqueue *_queue, struct nvkm_msgqueue_hdr *hdr)
u16 sw_managed_area_offset;
u16 sw_managed_area_size;
} *init = (void *)hdr;
+ const struct nvkm_falcon_func *func = _queue->falcon->func;
const struct nvkm_subdev *subdev = _queue->falcon->owner;
int i;
@@ -159,11 +160,13 @@ init_callback(struct nvkm_msgqueue *_queue, struct nvkm_msgqueue_hdr *hdr)
queue->size = init->queue_info[i].size;
if (i != MSGQUEUE_0137C63D_MESSAGE_QUEUE) {
- queue->head_reg = 0x4a0 + (queue->index * 4);
- queue->tail_reg = 0x4b0 + (queue->index * 4);
+ queue->head_reg = func->cmdq.head + queue->index *
+ func->cmdq.stride;
+ queue->tail_reg = func->cmdq.tail + queue->index *
+ func->cmdq.stride;
} else {
- queue->head_reg = 0x4c8;
- queue->tail_reg = 0x4cc;
+ queue->head_reg = func->msgq.head;
+ queue->tail_reg = func->msgq.tail;
}
nvkm_debug(subdev,
diff --git a/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0148cdec.c b/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0148cdec.c
index 9424803b9ef4..651bef2e3270 100644
--- a/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0148cdec.c
+++ b/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0148cdec.c
@@ -105,6 +105,7 @@ init_callback(struct nvkm_msgqueue *_queue, struct nvkm_msgqueue_hdr *hdr)
u16 sw_managed_area_offset;
u16 sw_managed_area_size;
} *init = (void *)hdr;
+ const struct nvkm_falcon_func *func = _queue->falcon->func;
const struct nvkm_subdev *subdev = _queue->falcon->owner;
int i;
@@ -129,11 +130,15 @@ init_callback(struct nvkm_msgqueue *_queue, struct nvkm_msgqueue_hdr *hdr)
queue->size = init->queue_info[i].size;
if (id == MSGQUEUE_0148CDEC_MESSAGE_QUEUE) {
- queue->head_reg = 0xa30 + (queue->index * 8);
- queue->tail_reg = 0xa34 + (queue->index * 8);
+ queue->head_reg = func->msgq.head + queue->index *
+ func->msgq.stride;
+ queue->tail_reg = func->msgq.tail + queue->index *
+ func->msgq.stride;
} else {
- queue->head_reg = 0xa00 + (queue->index * 8);
- queue->tail_reg = 0xa04 + (queue->index * 8);
+ queue->head_reg = func->cmdq.head + queue->index *
+ func->cmdq.stride;
+ queue->tail_reg = func->cmdq.tail + queue->index *
+ func->cmdq.stride;
}
nvkm_debug(subdev,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c
index 0e23325f94a7..88b909913ff9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c
@@ -255,6 +255,8 @@ gt215_pmu_flcn = {
.start = nvkm_falcon_v1_start,
.enable = nvkm_falcon_v1_enable,
.disable = nvkm_falcon_v1_disable,
+ .cmdq = { 0x4a0, 0x4b0, 4 },
+ .msgq = { 0x4c8, 0x4cc, 0 },
};
static const struct nvkm_pmu_func
--
2.28.0