From 16292bed9c56a20715d942fd5d9e025f01fa65fe Mon Sep 17 00:00:00 2001
From: Gayatri Kammela <gayatri.kammela@intel.com>
Date: Fri, 24 Jan 2020 10:59:28 -0800
Subject: [PATCH] platform/x86: intel_pmc_core: Add Atom based Jasper Lake (JSL) platform support
Git-commit: 16292bed9c56a20715d942fd5d9e025f01fa65fe
Patch-mainline: v5.7-rc1
References: jsc#SLE-13387
Add Jasper Lake to the list of the platforms that intel_pmc_core
driver supports for pmc_core device.
Just like Ice Lake, Tiger Lake and Elkhart Lake, Jasper Lake can also
reuse all the Cannon Lake PCH IPs. Also, it uses the same PCH IPs of
Tiger Lake, no additional effort is needed to enable but to simply reuse
them.
Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: David Box <david.e.box@intel.com>
Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Takashi Iwai <tiwai@suse.de>
---
drivers/platform/x86/intel_pmc_core.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
--- a/drivers/platform/x86/intel_pmc_core.c
+++ b/drivers/platform/x86/intel_pmc_core.c
@@ -193,7 +193,7 @@ static const struct pmc_bit_map cnp_pfea
{"Fuse", BIT(6)},
/*
* Reserved for Cannon Lake but valid for Ice Lake, Comet Lake,
- * Tiger Lake and Elkhart Lake.
+ * Tiger Lake, Elkhart Lake and Jasper Lake.
*/
{"SBR8", BIT(7)},
@@ -240,7 +240,7 @@ static const struct pmc_bit_map cnp_pfea
{"HDA_PGD6", BIT(4)},
/*
* Reserved for Cannon Lake but valid for Ice Lake, Comet Lake,
- * Tiger Lake and ELkhart Lake.
+ * Tiger Lake, ELkhart Lake and Jasper Lake.
*/
{"PSF6", BIT(5)},
{"PSF7", BIT(6)},
@@ -273,7 +273,7 @@ static const struct pmc_bit_map *ext_icl
};
static const struct pmc_bit_map tgl_pfear_map[] = {
- /* Tiger Lake and Elkhart Lake generation onwards only */
+ /* Tiger Lake, Elkhart Lake and Jasper Lake generation onwards only */
{"PSF9", BIT(0)},
{"RES_66", BIT(1)},
{"RES_67", BIT(2)},
@@ -883,6 +883,7 @@ static const struct x86_cpu_id intel_pmc
X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, &tgl_reg_map),
X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, &tgl_reg_map),
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, &tgl_reg_map),
+ X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, &tgl_reg_map),
{}
};