From bf3a3cdcad40e5928a22ea0fd200d17fd6d6308d Mon Sep 17 00:00:00 2001
From: Qinglang Miao <miaoqinglang@huawei.com>
Date: Fri, 30 Oct 2020 09:34:24 +0800
Subject: [PATCH] drm/tegra: sor: Disable clocks on error in tegra_sor_init()
Git-commit: bf3a3cdcad40e5928a22ea0fd200d17fd6d6308d
Patch-mainline: v5.10-rc7
References: git-fixes
Fix the missing clk_disable_unprepare() before return from
tegra_sor_init() in the error handling case.
Signed-off-by: Qinglang Miao <miaoqinglang@huawei.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Takashi Iwai <tiwai@suse.de>
---
drivers/gpu/drm/tegra/sor.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
--- a/drivers/gpu/drm/tegra/sor.c
+++ b/drivers/gpu/drm/tegra/sor.c
@@ -2896,6 +2896,7 @@ static int tegra_sor_init(struct host1x_
if (err < 0) {
dev_err(sor->dev, "failed to deassert SOR reset: %d\n",
err);
+ clk_disable_unprepare(sor->clk);
return err;
}
@@ -2903,12 +2904,17 @@ static int tegra_sor_init(struct host1x_
}
err = clk_prepare_enable(sor->clk_safe);
- if (err < 0)
+ if (err < 0) {
+ clk_disable_unprepare(sor->clk);
return err;
+ }
err = clk_prepare_enable(sor->clk_dp);
- if (err < 0)
+ if (err < 0) {
+ clk_disable_unprepare(sor->clk_safe);
+ clk_disable_unprepare(sor->clk);
return err;
+ }
/*
* Enable and unmask the HDA codec SCRATCH0 register interrupt. This