From: Vladimir Oltean <vladimir.oltean@nxp.com>
Date: Sun, 23 Feb 2020 22:47:11 +0200
Subject: arm64: dts: ls1028a: delete extraneous #interrupt-cells for ENETC RCIE
Git-commit: 8023321d30be83cb9a9ef57376fa5a9c7c8bd887
Patch-mainline: v5.7-rc1
References: bsc#1175012
This specifier overrides the interrupt specifier with 3 cells from gic
(/interrupt-controller@6000000), but in fact ENETC is not an interrupt
controller, so the property is bogus.
Interrupts used by the children of the ENETC RCIE must use the full
3-cell specifier required by the GIC.
The issue has no functional consequence so there is no real reason to
port the patch to stable trees.
Fixes: 927d7f857542 ("arm64: dts: fsl: ls1028a: Add PCI IERC node and ENETC endpoints")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Tested-by: Michael Walle <michael@walle.cc>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 8694098aa94b..6e406a6a16cf 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -722,7 +722,6 @@ pcie@1f0000000 { /* Integrated Endpoint Root Complex */
reg = <0x01 0xf0000000 0x0 0x100000>;
#address-cells = <3>;
#size-cells = <2>;
- #interrupt-cells = <1>;
msi-parent = <&its>;
device_type = "pci";
bus-range = <0x0 0x0>;
--
2.28.0