From 18afcf90d8807fef66d1fd428eeb2b407df90fa8 Mon Sep 17 00:00:00 2001
From: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Date: Mon, 22 Aug 2022 21:00:44 +0200
Subject: [PATCH] ALSA: hda: cleanup definitions for multi-link registers
Git-commit: 18afcf90d8807fef66d1fd428eeb2b407df90fa8
Patch-mainline: v6.1-rc1
References: jsc#PED-850
For some reason two masks are used without the AZX prefix, and the
pattern MLCLT should be ML_LCTL for consistency.
Pure rename, no functionality change.
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Link: https://lore.kernel.org/r/20220822190044.170495-1-pierre-louis.bossart@linux.intel.com
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
include/sound/hda_register.h | 20 +++++++++++---------
sound/hda/ext/hdac_ext_controller.c | 16 ++++++++--------
sound/pci/hda/hda_intel.c | 14 +++++++-------
3 files changed, 26 insertions(+), 24 deletions(-)
diff --git a/include/sound/hda_register.h b/include/sound/hda_register.h
index ad8b71b1dbb6..d37cf43546eb 100644
--- a/include/sound/hda_register.h
+++ b/include/sound/hda_register.h
@@ -260,7 +260,18 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
#define AZX_REG_ML_LCAP 0x00
#define AZX_REG_ML_LCTL 0x04
+
+#define AZX_ML_LCTL_CPA BIT(23)
+#define AZX_ML_LCTL_CPA_SHIFT 23
+#define AZX_ML_LCTL_SPA BIT(16)
+#define AZX_ML_LCTL_SPA_SHIFT 16
+#define AZX_ML_LCTL_SCF GENMASK(3, 0)
+
#define AZX_REG_ML_LOSIDV 0x08
+
+/* bit0 is reserved, with BIT(1) mapping to stream1 */
+#define AZX_ML_LOSIDV_STREAM_MASK 0xFFFE
+
#define AZX_REG_ML_LSDIID 0x0C
#define AZX_REG_ML_LPSOO 0x10
#define AZX_REG_ML_LPSIO 0x12
@@ -268,15 +279,6 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
#define AZX_REG_ML_LOUTPAY 0x20
#define AZX_REG_ML_LINPAY 0x30
-/* bit0 is reserved, with BIT(1) mapping to stream1 */
-#define ML_LOSIDV_STREAM_MASK 0xFFFE
-
-#define ML_LCTL_SCF_MASK 0xF
-#define AZX_MLCTL_SPA (0x1 << 16)
-#define AZX_MLCTL_CPA (0x1 << 23)
-#define AZX_MLCTL_SPA_SHIFT 16
-#define AZX_MLCTL_CPA_SHIFT 23
-
/* registers for DMA Resume Capability Structure */
#define AZX_DRSM_CAP_ID 0x5
#define AZX_REG_DRSM_CTL 0x4
diff --git a/sound/hda/ext/hdac_ext_controller.c b/sound/hda/ext/hdac_ext_controller.c
index a42f66f561f5..80876b9a87f4 100644
--- a/sound/hda/ext/hdac_ext_controller.c
+++ b/sound/hda/ext/hdac_ext_controller.c
@@ -170,7 +170,7 @@ static int check_hdac_link_power_active(struct hdac_ext_link *link, bool enable)
{
int timeout;
u32 val;
- int mask = (1 << AZX_MLCTL_CPA_SHIFT);
+ int mask = (1 << AZX_ML_LCTL_CPA_SHIFT);
udelay(3);
timeout = 150;
@@ -178,10 +178,10 @@ static int check_hdac_link_power_active(struct hdac_ext_link *link, bool enable)
do {
val = readl(link->ml_addr + AZX_REG_ML_LCTL);
if (enable) {
- if (((val & mask) >> AZX_MLCTL_CPA_SHIFT))
+ if (((val & mask) >> AZX_ML_LCTL_CPA_SHIFT))
return 0;
} else {
- if (!((val & mask) >> AZX_MLCTL_CPA_SHIFT))
+ if (!((val & mask) >> AZX_ML_LCTL_CPA_SHIFT))
return 0;
}
udelay(3);
@@ -197,7 +197,7 @@ static int check_hdac_link_power_active(struct hdac_ext_link *link, bool enable)
int snd_hdac_ext_bus_link_power_up(struct hdac_ext_link *link)
{
snd_hdac_updatel(link->ml_addr, AZX_REG_ML_LCTL,
- AZX_MLCTL_SPA, AZX_MLCTL_SPA);
+ AZX_ML_LCTL_SPA, AZX_ML_LCTL_SPA);
return check_hdac_link_power_active(link, true);
}
@@ -209,7 +209,7 @@ EXPORT_SYMBOL_GPL(snd_hdac_ext_bus_link_power_up);
*/
int snd_hdac_ext_bus_link_power_down(struct hdac_ext_link *link)
{
- snd_hdac_updatel(link->ml_addr, AZX_REG_ML_LCTL, AZX_MLCTL_SPA, 0);
+ snd_hdac_updatel(link->ml_addr, AZX_REG_ML_LCTL, AZX_ML_LCTL_SPA, 0);
return check_hdac_link_power_active(link, false);
}
@@ -226,7 +226,7 @@ int snd_hdac_ext_bus_link_power_up_all(struct hdac_bus *bus)
list_for_each_entry(hlink, &bus->hlink_list, list) {
snd_hdac_updatel(hlink->ml_addr, AZX_REG_ML_LCTL,
- AZX_MLCTL_SPA, AZX_MLCTL_SPA);
+ AZX_ML_LCTL_SPA, AZX_ML_LCTL_SPA);
ret = check_hdac_link_power_active(hlink, true);
if (ret < 0)
return ret;
@@ -247,7 +247,7 @@ int snd_hdac_ext_bus_link_power_down_all(struct hdac_bus *bus)
list_for_each_entry(hlink, &bus->hlink_list, list) {
snd_hdac_updatel(hlink->ml_addr, AZX_REG_ML_LCTL,
- AZX_MLCTL_SPA, 0);
+ AZX_ML_LCTL_SPA, 0);
ret = check_hdac_link_power_active(hlink, false);
if (ret < 0)
return ret;
@@ -281,7 +281,7 @@ int snd_hdac_ext_bus_link_get(struct hdac_bus *bus,
* clear the register to invalidate all the output streams
*/
snd_hdac_updatew(link->ml_addr, AZX_REG_ML_LOSIDV,
- ML_LOSIDV_STREAM_MASK, 0);
+ AZX_ML_LOSIDV_STREAM_MASK, 0);
/*
* wait for 521usec for codec to report status
* HDA spec section 4.3 - Codec Discovery
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index 7720978dc132..bf9df9bc8f1b 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -489,14 +489,14 @@ static int intel_ml_lctl_set_power(struct azx *chip, int state)
* If other links are enabled for stream, they need similar fix
*/
val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
- val &= ~AZX_MLCTL_SPA;
- val |= state << AZX_MLCTL_SPA_SHIFT;
+ val &= ~AZX_ML_LCTL_SPA;
+ val |= state << AZX_ML_LCTL_SPA_SHIFT;
writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
/* wait for CPA */
timeout = 50;
while (timeout) {
if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
- AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
+ AZX_ML_LCTL_CPA) == (state << AZX_ML_LCTL_CPA_SHIFT))
return 0;
timeout--;
udelay(10);
@@ -514,15 +514,15 @@ static void intel_init_lctl(struct azx *chip)
/* 0. check lctl register value is correct or not */
val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
/* if SCF is already set, let's use it */
- if ((val & ML_LCTL_SCF_MASK) != 0)
+ if ((val & AZX_ML_LCTL_SCF) != 0)
return;
/*
* Before operating on SPA, CPA must match SPA.
* Any deviation may result in undefined behavior.
*/
- if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
- ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
+ if (((val & AZX_ML_LCTL_SPA) >> AZX_ML_LCTL_SPA_SHIFT) !=
+ ((val & AZX_ML_LCTL_CPA) >> AZX_ML_LCTL_CPA_SHIFT))
return;
/* 1. turn link down: set SPA to 0 and wait CPA to 0 */
@@ -532,7 +532,7 @@ static void intel_init_lctl(struct azx *chip)
goto set_spa;
/* 2. update SCF to select a properly audio clock*/
- val &= ~ML_LCTL_SCF_MASK;
+ val &= ~AZX_ML_LCTL_SCF;
val |= intel_get_lctl_scf(chip);
writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
--
2.35.3