From: Alex Deucher <alexander.deucher@amd.com>
Date: Tue, 13 Feb 2018 14:37:36 -0500
Subject: drm/amdgpu/powerplay/smu7: drop refresh rate checks for mclk switching
Git-commit: d821792171a0457431dd57f0f2b8828c478b26ab
Patch-mainline: v4.17-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166
The logic has moved to cgs. mclk switching with DC at higher refresh
rates should work.
Reviewed-by: Eric Huang <JinhuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -2909,8 +2909,7 @@ static int smu7_apply_state_adjust_rules
else
disable_mclk_switching = ((1 < info.display_count) ||
disable_mclk_switching_for_frame_lock ||
- smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us) ||
- (mode_info.refresh_rate > 120));
+ smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us));
sclk = smu7_ps->performance_levels[0].engine_clock;
mclk = smu7_ps->performance_levels[0].memory_clock;