From 32087d1425887e2d51e8c77ff9849d73f6384457 Mon Sep 17 00:00:00 2001
From: Praveen Paneri <praveen.paneri@intel.com>
Date: Thu, 3 Aug 2017 23:02:10 +0530
Subject: [PATCH] drm/i915: enable WaDisableDopClkGating for skl
Git-commit: 32087d1425887e2d51e8c77ff9849d73f6384457
Patch-mainline: v4.14-rc1
References: FATE#322643 bsc#1055900
This WA is required when decoupled frequencies for slice and unslice
are enabled. This disables DOP clock gating for skl.
V2: enable the WA for all gen9 platforms (not just for SKL GT4 where the hang issue is originally reported) to avoid rare hangs (David)
V3: as per WaDatabase, enable it only for SKL (Rodrigo)
Cc: David Weinehall <david.weinehall@linux.intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1501781530-8186-1-git-send-email-praveen.paneri@intel.com
Acked-by: Takashi Iwai <tiwai@suse.de>
---
drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
1 file changed, 6 insertions(+)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -78,6 +78,12 @@ static void gen9_init_clock_gating(struc
/* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
ILK_DPFC_DISABLE_DUMMY0);
+
+ if (IS_SKYLAKE(dev_priv)) {
+ /* WaDisableDopClockGating */
+ I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL)
+ & ~GEN7_DOP_CLOCK_GATE_ENABLE);
+ }
}
static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)