From: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
Date: Wed, 8 Mar 2023 13:36:17 +0100
Subject: [PATCH] arm64: dts: qcom: msm8916: Fix tsens_mode unit address
References: bsc#1012628
Patch-mainline: 6.3.2
Git-commit: 608465f798bb3eaf6773a49b893902860858e294
[ Upstream commit 608465f798bb3eaf6773a49b893902860858e294 ]
The reg address of the tsens_mode nvmem cell is correct but the unit
address does not match (0xec vs 0xef). Fix it. No functional change.
Fixes: 24aafd041fb2 ("arm64: dts: qcom: msm8916: specify per-sensor calibration cells")
Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308123617.101211-1-stephan.gerhold@kernkonzept.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Jiri Slaby <jslaby@suse.cz>
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 0733c2f4..0d528380 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -503,7 +503,7 @@ tsens_base2: base2@d7 {
bits = <1 7>;
};
- tsens_mode: mode@ec {
+ tsens_mode: mode@ef {
reg = <0xef 0x1>;
bits = <5 3>;
};
--
2.35.3