From f45403fc7aabdd9dfa79a87b479c33e95251a021 Mon Sep 17 00:00:00 2001
From: Takashi Iwai <tiwai@suse.de>
Date: Wed, 21 Apr 2021 13:12:48 +0200
Subject: [PATCH 11/11] drm/ast: Add 25MHz refclk support
Patch-mainline: Never, temporary fixes until upstream resolution
References: bsc#1174416

A code snippet forward-ported from A-Speed downstream driver.

Signed-off-by: Takashi Iwai <tiwai@suse.de>

---
 drivers/gpu/drm/ast/ast_drv.h    |    1 
 drivers/gpu/drm/ast/ast_mode.c   |   15 +++++++--
 drivers/gpu/drm/ast/ast_tables.h |   60 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 72 insertions(+), 4 deletions(-)

--- a/drivers/gpu/drm/ast/ast_drv.h
+++ b/drivers/gpu/drm/ast/ast_drv.h
@@ -106,6 +106,7 @@ struct ast_private {
 	struct drm_gem_object *cursor_cache;
 	int next_cursor;
 	bool support_newvga_mode;
+	bool refclk_25mhz;
 	enum {
 		ast_use_p2a,
 		ast_use_dt,
--- a/drivers/gpu/drm/ast/ast_mode.c
+++ b/drivers/gpu/drm/ast/ast_mode.c
@@ -402,10 +402,17 @@ static void ast_set_dclk_reg(struct drm_
 	struct ast_private *ast = dev->dev_private;
 	const struct ast_vbios_dclk_info *clk_info;
 
-	if (ast->chip == AST2500)
-		clk_info = &dclk_table_ast2500[vbios_mode->enh_table->dclk_index];
-	else
-		clk_info = &dclk_table[vbios_mode->enh_table->dclk_index];
+	if (ast->chip == AST2500) {
+		if (ast->refclk_25mhz)
+			clk_info = &dclk_table_ast2500_25mhz[vbios_mode->enh_table->dclk_index];
+		else
+			clk_info = &dclk_table_ast2500[vbios_mode->enh_table->dclk_index];
+	} else {
+		if (ast->refclk_25mhz)
+			clk_info = &dclk_table_25mhz[vbios_mode->enh_table->dclk_index];
+		else
+			clk_info = &dclk_table[vbios_mode->enh_table->dclk_index];
+	}
 
 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1);
 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2);
--- a/drivers/gpu/drm/ast/ast_tables.h
+++ b/drivers/gpu/drm/ast/ast_tables.h
@@ -109,6 +109,36 @@ static const struct ast_vbios_dclk_info
 	{0x3b, 0x2c, 0x81},			/* 1A: VCLK118_25	*/
 };
 
+static const struct ast_vbios_dclk_info dclk_table_25mhz[] = {
+	{0x2C, 0xE7, 0x03},			/* 00: VCLK25_175	*/
+	{0x95, 0x62, 0x03},			/* 01: VCLK28_322	*/
+	{0x67, 0x63, 0x01},			/* 02: VCLK31_5         */
+	{0x76, 0x63, 0x01},			/* 03: VCLK36		*/
+	{0xEE, 0x67, 0x01},			/* 04: VCLK40		*/
+	{0x82, 0x62, 0x01},			/* 05: VCLK49_5		*/
+	{0xC6, 0x64, 0x01},			/* 06: VCLK50		*/
+	{0x94, 0x62, 0x01},			/* 07: VCLK56_25	*/
+	{0x80, 0x64, 0x00},			/* 08: VCLK65		*/
+	{0x7B, 0x63, 0x00},			/* 09: VCLK75		*/
+	{0x67, 0x62, 0x00},			/* 0A: VCLK78_75	*/
+	{0x7C, 0x62, 0x00},			/* 0B: VCLK94_5		*/
+	{0x8E, 0x62, 0x00},			/* 0C: VCLK108		*/
+	{0x85, 0x24, 0x00},			/* 0D: VCLK135		*/
+	{0x67, 0x22, 0x00},			/* 0E: VCLK157_5	*/
+	{0x6A, 0x22, 0x00},			/* 0F: VCLK162		*/
+	{0x25, 0x46, 0x80},			/* 10: VCLK154		*/
+	{0x14, 0x63, 0x80},			/* 11: VCLK83.5         */
+	{0x11, 0x44, 0x80},			/* 12: VCLK106.5        */
+	{0x23, 0x46, 0x80},			/* 13: VCLK146.25       */
+	{0x4d, 0x4d, 0x80},			/* 14: VCLK148.5        */
+	{0x11, 0x63, 0x80},			/* 15: VCLK71           */
+	{0x47, 0x6a, 0x80},			/* 16: VCLK88.75        */
+	{0x13, 0x44, 0x80},			/* 17: VCLK119          */
+	{0x29, 0x66, 0x80},		        /* 18: VCLK85_5         */
+	{0x2f, 0x66, 0x80},			/* 19: VCLK97_75        */
+	{0x21, 0x47, 0x80},			/* 1A: VCLK118_25       */
+};
+
 static const struct ast_vbios_dclk_info dclk_table_ast2500[] = {
 	{0x2C, 0xE7, 0x03},			/* 00: VCLK25_175	*/
 	{0x95, 0x62, 0x03},			/* 01: VCLK28_322	*/
@@ -139,6 +169,36 @@ static const struct ast_vbios_dclk_info
 	{0x44, 0x20, 0x43},			/* 1A: VCLK118_25	*/
 };
 
+static const struct ast_vbios_dclk_info dclk_table_ast2500_25mhz[] = {
+	{0x2C, 0xE7, 0x03},			/* 00: VCLK25_175	*/
+	{0x95, 0x62, 0x03},			/* 01: VCLK28_322	*/
+	{0x67, 0x63, 0x01},			/* 02: VCLK31_5         */
+	{0x76, 0x63, 0x01},			/* 03: VCLK36		*/
+	{0xEE, 0x67, 0x01},			/* 04: VCLK40		*/
+	{0x82, 0x62, 0x01},			/* 05: VCLK49_5		*/
+	{0xC6, 0x64, 0x01},			/* 06: VCLK50		*/
+	{0x94, 0x62, 0x01},			/* 07: VCLK56_25	*/
+	{0x80, 0x64, 0x00},			/* 08: VCLK65		*/
+	{0x7B, 0x63, 0x00},			/* 09: VCLK75		*/
+	{0x67, 0x62, 0x00},			/* 0A: VCLK78_75	*/
+	{0x7C, 0x62, 0x00},			/* 0B: VCLK94_5		*/
+	{0x8E, 0x62, 0x00},			/* 0C: VCLK108		*/
+	{0x85, 0x24, 0x00},			/* 0D: VCLK135		*/
+	{0x67, 0x22, 0x00},			/* 0E: VCLK157_5	*/
+	{0x6A, 0x22, 0x00},			/* 0F: VCLK162		*/
+	{0x4d, 0x4c, 0x80},			/* 10: VCLK154		*/
+	{0x68, 0x6f, 0x80},			/* 11: VCLK83.5         */
+	{0x28, 0x49, 0x80},			/* 12: VCLK106.5        */
+	{0x37, 0x49, 0x80},			/* 13: VCLK146.25       */
+	{0x1f, 0x45, 0x80},			/* 14: VCLK148.5        */
+	{0x47, 0x6c, 0x80},			/* 15: VCLK71           */
+	{0x25, 0x65, 0x80},			/* 16: VCLK88.75        */
+	{0x38, 0x60, 0x42},			/* 17: VCLK119          */
+	{0x32, 0x67, 0x80},		        /* 18: VCLK85_5         */
+	{0x6a, 0x6d, 0x80},			/* 19: VCLK97_75        */
+	{0x41, 0x20, 0x43},			/* 1A: VCLK118_25       */
+};
+
 static const struct ast_vbios_stdtable vbios_stdtable[] = {
 	/* MD_2_3_400 */
 	{