From: James Morse <james.morse@arm.com>
Date: Thu, 17 Oct 2019 18:43:00 +0100
Subject: arm64: compat: Workaround Neoverse-N1 #1542419 for compat user-space
Git-commit: 222fc0c8503d98cec3cb2bac2780cdd21a6e31c0
Patch-mainline: v5.5-rc1
References: jsc#ECO-561,jsc#SLE-10671
Compat user-space is unable to perform ICIMVAU instructions from
user-space. Instead it uses a compat-syscall. Add the workaround for
Neoverse-N1 #1542419 to this code path.
Signed-off-by: James Morse <james.morse@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
---
arch/arm64/kernel/sys_compat.c | 11 +++++++++++
1 file changed, 11 insertions(+)
--- a/arch/arm64/kernel/sys_compat.c
+++ b/arch/arm64/kernel/sys_compat.c
@@ -19,6 +19,7 @@
*/
#include <linux/compat.h>
+#include <linux/cpufeature.h>
#include <linux/personality.h>
#include <linux/sched.h>
#include <linux/sched/signal.h>
@@ -27,6 +28,7 @@
#include <linux/uaccess.h>
#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
#include <asm/unistd.h>
static long
@@ -40,6 +42,15 @@ __do_compat_cache_op(unsigned long start
if (fatal_signal_pending(current))
return 0;
+ if (cpus_have_const_cap(ARM64_WORKAROUND_1542419)) {
+ /*
+ * The workaround requires an inner-shareable tlbi.
+ * We pick the reserved-ASID to minimise the impact.
+ */
+ __tlbi(aside1is, 0);
+ dsb(ish);
+ }
+
ret = __flush_cache_user_range(start, start + chunk);
if (ret)
return ret;