From: Yongqiang Sun <yongqiang.sun@amd.com>
Date: Thu, 22 Feb 2018 16:50:39 -0500
Subject: drm/amd/display: Remove 300Mhz minimum disp clk limit.
Git-commit: 623a7e96cd73a46d15f64b1c5e1f4ea3548271f2
Patch-mainline: v4.17-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166
300Mhz disp clk limit was a workaround that was fixed in SMU and is no
longer needed.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 5 +++++
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 3 ---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 --
3 files changed, 5 insertions(+), 5 deletions(-)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -803,6 +803,8 @@ static enum dc_status dc_commit_state_no
if (!dcb->funcs->is_accelerated_mode(dcb))
dc->hwss.enable_accelerated_mode(dc, context);
+ dc->hwss.set_bandwidth(dc, context, false);
+
/* re-program planes for existing stream, in case we need to
* free up plane resource for later use
*/
@@ -869,6 +871,9 @@ static enum dc_status dc_commit_state_no
context->streams[i]->timing.pix_clk_khz);
}
+ /* pplib is notified if disp_num changed */
+ dc->hwss.set_bandwidth(dc, context, true);
+
dc_enable_stereo(dc, context, dc_streams, context->stream_count);
dc_release_state(dc->current_state);
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -2106,9 +2106,6 @@ enum dc_status dce110_apply_ctx_to_hw(
return status;
}
- /* pplib is notified if disp_num changed */
- dc->hwss.set_bandwidth(dc, context, true);
-
/* to save power */
apply_min_clocks(dc, context, &clocks_state, false);
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -440,8 +440,6 @@ static const struct dc_debug debug_defau
.timing_trace = false,
.clock_trace = true,
- .min_disp_clk_khz = 300000,
-
.disable_pplib_clock_request = true,
.disable_pplib_wm_range = false,
.pplib_wm_report_mode = WM_REPORT_DEFAULT,