From: shameer <shameerali.kolothum.thodi@huawei.com>
Date: Wed, 17 May 2017 10:12:05 +0100
Subject: iommu/arm-smmu-v3: Enable ACPI based HiSilicon CMD_PREFETCH
quirk(erratum 161010701)
Patch-mainline: v4.13-rc1
Git-commit: 99caf177f6fd3e67575f6ce05b36e8e041bcef60
References: FATE#323954
HiSilicon SMMUv3 on Hip06/Hip07 platforms doesn't support CMD_PREFETCH
command. The dt based support for this quirk is already present in the
driver(hisilicon,broken-prefetch-cmd). This adds ACPI support for the
quirk using the IORT smmu model number.
Signed-off-by: shameer <shameerali.kolothum.thodi@huawei.com>
Signed-off-by: hanjun <guohanjun@huawei.com>
[will: rewrote patch]
Signed-off-by: Will Deacon <will.deacon@arm.com>
Acked-by: Alexander Graf <agraf@suse.de>
---
Documentation/arm64/silicon-errata.txt | 1 +
drivers/iommu/arm-smmu-v3.c | 12 +++++++++++-
2 files changed, 12 insertions(+), 1 deletion(-)
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -68,6 +68,7 @@ stable kernels.
| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 |
| | | | |
| Hisilicon | Hip0{5,6,7} | #161010101 | HISILICON_ERRATUM_161010101 |
+| Hisilicon | Hip0{6,7} | #161010701 | N/A |
| | | | |
| Qualcomm Tech. | Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 |
| Qualcomm Tech. | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 |
--- a/drivers/iommu/arm-smmu-v3.c
+++ b/drivers/iommu/arm-smmu-v3.c
@@ -418,6 +418,10 @@
#define ACPI_IORT_SMMU_V3_CAVIUM_CN99XX 0x2
#endif
+#ifndef ACPI_IORT_SMMU_HISILICON_HI161X
+#define ACPI_IORT_SMMU_HISILICON_HI161X 0x1
+#endif
+
static bool disable_bypass;
module_param_named(disable_bypass, disable_bypass, bool, S_IRUGO);
MODULE_PARM_DESC(disable_bypass,
@@ -2616,8 +2620,14 @@ static int arm_smmu_device_hw_probe(stru
#ifdef CONFIG_ACPI
static void acpi_smmu_get_options(u32 model, struct arm_smmu_device *smmu)
{
- if (model == ACPI_IORT_SMMU_V3_CAVIUM_CN99XX)
+ switch (model) {
+ case ACPI_IORT_SMMU_V3_CAVIUM_CN99XX:
smmu->options |= ARM_SMMU_OPT_PAGE0_REGS_ONLY;
+ break;
+ case ACPI_IORT_SMMU_HISILICON_HI161X:
+ smmu->options |= ARM_SMMU_OPT_SKIP_PREFETCH;
+ break;
+ }
dev_notice(smmu->dev, "option mask 0x%x\n", smmu->options);
}