From: Marc Zyngier <maz@kernel.org>
Date: Wed, 9 Mar 2022 18:06:00 +0000
Subject: arm64: Add cavium_erratum_23154_cpus missing sentinel
Git-commit: f90205b95368ee2b56fc523abda6c4d514901d9b
Patch-mainline: v5.18-rc1
References: jsc#SLE-24682

Qian Cai reported that playing with CPU hotplug resulted in a
out-of-bound access due to cavium_erratum_23154_cpus missing
a sentinel indicating the end of the array.

Add it in order to restore peace and harmony in the world
of broken HW.

Reported-by: Qian Cai <quic_qiancai@quicinc.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Fixes: 24a147bcef8c ("irqchip/gic-v3: Workaround Marvell erratum 38545 when reading IAR")
Link: https://lore.kernel.org/r/YijmkXp1VG7e8lDx@qian
Cc: Linu Cherian <lcherian@marvell.com>
Cc: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/r/20220309180600.3990874-1-maz@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
---
 arch/arm64/kernel/cpu_errata.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 510f47055b91..6485d8e54cca 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -225,6 +225,7 @@ const struct midr_range cavium_erratum_23154_cpus[] = {
 	MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXN),
 	MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXMM),
 	MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXO),
+	{},
 };
 #endif
 
-- 
2.36.0