From: Tony Cheng <tony.cheng@amd.com>
Date: Tue, 26 Sep 2017 10:16:34 -0400
Subject: drm/amd/display: fix bug in force_single_disp_pipe_split
Git-commit: 9f945eab797b042930553388d37c12fed38f3396
Patch-mainline: v4.15-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166
should only lower dpp clock.
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -732,11 +732,14 @@ void hack_disable_optional_pipe_split(st
void hack_force_pipe_split(struct dcn_bw_internal_vars *v,
unsigned int pixel_rate_khz)
{
+ float pixel_rate_mhz = pixel_rate_khz / 1000;
+
/*
* force enabling pipe split by lower dpp clock for DPM0 to just
* below the specify pixel_rate, so bw calc would split pipe.
*/
- v->max_dppclk[0] = pixel_rate_khz / 1000;
+ if (pixel_rate_mhz < v->max_dppclk[0])
+ v->max_dppclk[0] = pixel_rate_mhz;
}
void hack_bounding_box(struct dcn_bw_internal_vars *v,