From: Tony Cheng <tony.cheng@amd.com>
Date: Tue, 16 May 2017 21:27:01 -0400
Subject: drm/amd/display: read VM settings from MMHUB
Git-commit: 1f7f3aec125724da30ff1c2f2d359340feb0d9e1
Patch-mainline: v4.15-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166
instead of GC, as after GFX off, GC can be power gated any time
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 24 ++++++++---------
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 14 ++++-----
2 files changed, 19 insertions(+), 19 deletions(-)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
@@ -130,18 +130,18 @@
SR(DCHUBBUB_ARB_SAT_LEVEL),\
SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\
/* todo: get these from GVM instead of reading registers ourselves */\
- GC_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\
- GC_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\
- GC_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),\
- GC_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),\
- GC_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),\
- GC_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),\
- GC_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),\
- GC_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),\
- GC_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\
- GC_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),\
- GC_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\
- GC_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR)
+ MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\
+ MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\
+ MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),\
+ MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),\
+ MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),\
+ MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),\
+ MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),\
+ MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),\
+ MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\
+ MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),\
+ MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\
+ MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR)
struct dcn_mi_registers {
uint32_t DCHUBP_CNTL;
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -122,15 +122,15 @@ enum dcn10_clk_src_array_id {
.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
mm ## reg_name
-/* GC */
-#define GC_BASE_INNER(seg) \
- GC_BASE__INST0_SEG ## seg
+/* MMHUB */
+#define MMHUB_BASE_INNER(seg) \
+ MMHUB_BASE__INST0_SEG ## seg
-#define GC_BASE(seg) \
- GC_BASE_INNER(seg)
+#define MMHUB_BASE(seg) \
+ MMHUB_BASE_INNER(seg)
-#define GC_SR(reg_name)\
- .reg_name = GC_BASE(mm ## reg_name ## _BASE_IDX) + \
+#define MMHUB_SR(reg_name)\
+ .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
mm ## reg_name
/* macros to expend register list macro defined in HW object header file