From: Alex Deucher <alexander.deucher@amd.com>
Date: Wed, 16 May 2018 08:39:58 -0500
Subject: drm/amdgpu/display: remove VEGAM config option
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Git-commit: 2b6dc93a3d439136c3fe11291a506e581b84a327
Patch-mainline: v4.18-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166
Leftover from bringup. No need to keep it around for
upstream.
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
drivers/gpu/drm/amd/display/Kconfig | 7 -------
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ----
drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c | 2 --
drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c | 2 --
drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 4 ----
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 4 ----
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 4 ----
drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 2 --
drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 2 --
drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 2 --
drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h | 2 --
drivers/gpu/drm/amd/display/include/dal_asic_id.h | 6 +-----
drivers/gpu/drm/amd/display/include/dal_types.h | 2 --
13 files changed, 1 insertion(+), 42 deletions(-)
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -34,13 +34,6 @@ config DEBUG_KERNEL_DC
if you want to hit
kdgb_break in assert.
-config DRM_AMD_DC_VEGAM
- bool "VEGAM support"
- depends on DRM_AMD_DC
- help
- Choose this option if you want to have
- VEGAM support for display engine
-
config DRM_AMD_DC_VG20
bool "Vega20 support"
depends on DRM_AMD_DC
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1514,9 +1514,7 @@ static int amdgpu_dm_initialize_drm_devi
case CHIP_POLARIS11:
case CHIP_POLARIS10:
case CHIP_POLARIS12:
-#if defined(CONFIG_DRM_AMD_DC_VEGAM)
case CHIP_VEGAM:
-#endif
case CHIP_VEGA10:
case CHIP_VEGA12:
case CHIP_VEGA20:
@@ -1710,9 +1708,7 @@ static int dm_early_init(void *handle)
adev->mode_info.plane_type = dm_plane_type_default;
break;
case CHIP_POLARIS10:
-#if defined(CONFIG_DRM_AMD_DC_VEGAM)
case CHIP_VEGAM:
-#endif
adev->mode_info.num_crtc = 6;
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 6;
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
@@ -51,9 +51,7 @@ bool dal_bios_parser_init_cmd_tbl_helper
return true;
case DCE_VERSION_11_2:
-#if defined(CONFIG_DRM_AMD_DC_VEGAM)
case DCE_VERSION_11_22:
-#endif
*h = dal_cmd_tbl_helper_dce112_get_table();
return true;
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
@@ -52,9 +52,7 @@ bool dal_bios_parser_init_cmd_tbl_helper
return true;
case DCE_VERSION_11_2:
-#if defined(CONFIG_DRM_AMD_DC_VEGAM)
case DCE_VERSION_11_22:
-#endif
*h = dal_cmd_tbl_helper_dce112_get_table2();
return true;
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
--- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
@@ -59,10 +59,8 @@ static enum bw_calcs_version bw_calcs_ve
return BW_CALCS_VERSION_POLARIS10;
if (ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev))
return BW_CALCS_VERSION_POLARIS11;
-#if defined(CONFIG_DRM_AMD_DC_VEGAM)
if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
return BW_CALCS_VERSION_VEGAM;
-#endif
return BW_CALCS_VERSION_INVALID;
case FAMILY_AI:
@@ -2151,11 +2149,9 @@ void bw_calcs_init(struct bw_calcs_dceip
dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0); /* todo: this is a bug*/
break;
case BW_CALCS_VERSION_POLARIS10:
-#if defined(CONFIG_DRM_AMD_DC_VEGAM)
/* TODO: Treat VEGAM the same as P10 for now
* Need to tune the para for VEGAM if needed */
case BW_CALCS_VERSION_VEGAM:
-#endif
vbios.memory_type = bw_def_gddr5;
vbios.dram_channel_width_in_bits = 32;
vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -79,10 +79,8 @@ enum dce_version resource_parse_asic_id(
ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
dc_version = DCE_VERSION_11_2;
}
-#if defined(CONFIG_DRM_AMD_DC_VEGAM)
if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
dc_version = DCE_VERSION_11_22;
-#endif
break;
case FAMILY_AI:
dc_version = DCE_VERSION_12_0;
@@ -129,9 +127,7 @@ struct resource_pool *dc_create_resource
num_virtual_links, dc, asic_id);
break;
case DCE_VERSION_11_2:
-#if defined(CONFIG_DRM_AMD_DC_VEGAM)
case DCE_VERSION_11_22:
-#endif
res_pool = dce112_create_resource_pool(
num_virtual_links, dc);
break;
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -590,9 +590,7 @@ static uint32_t dce110_get_pix_clk_divid
pll_settings, pix_clk_params);
break;
case DCE_VERSION_11_2:
-#if defined(CONFIG_DRM_AMD_DC_VEGAM)
case DCE_VERSION_11_22:
-#endif
case DCE_VERSION_12_0:
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case DCN_VERSION_1_0:
@@ -982,9 +980,7 @@ static bool dce110_program_pix_clk(
break;
case DCE_VERSION_11_2:
-#if defined(CONFIG_DRM_AMD_DC_VEGAM)
case DCE_VERSION_11_22:
-#endif
case DCE_VERSION_12_0:
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case DCN_VERSION_1_0:
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
@@ -75,9 +75,7 @@ bool dal_hw_factory_init(
return true;
case DCE_VERSION_11_0:
case DCE_VERSION_11_2:
-#if defined(CONFIG_DRM_AMD_DC_VEGAM)
case DCE_VERSION_11_22:
-#endif
dal_hw_factory_dce110_init(factory);
return true;
case DCE_VERSION_12_0:
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
@@ -72,9 +72,7 @@ bool dal_hw_translate_init(
case DCE_VERSION_10_0:
case DCE_VERSION_11_0:
case DCE_VERSION_11_2:
-#if defined(CONFIG_DRM_AMD_DC_VEGAM)
case DCE_VERSION_11_22:
-#endif
dal_hw_translate_dce110_init(translate);
return true;
case DCE_VERSION_12_0:
--- a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
@@ -83,9 +83,7 @@ struct i2caux *dal_i2caux_create(
case DCE_VERSION_8_3:
return dal_i2caux_dce80_create(ctx);
case DCE_VERSION_11_2:
-#if defined(CONFIG_DRM_AMD_DC_VEGAM)
case DCE_VERSION_11_22:
-#endif
return dal_i2caux_dce112_create(ctx);
case DCE_VERSION_11_0:
return dal_i2caux_dce110_create(ctx);
--- a/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h
@@ -43,9 +43,7 @@ enum bw_calcs_version {
BW_CALCS_VERSION_POLARIS10,
BW_CALCS_VERSION_POLARIS11,
BW_CALCS_VERSION_POLARIS12,
-#if defined(CONFIG_DRM_AMD_DC_VEGAM)
BW_CALCS_VERSION_VEGAM,
-#endif
BW_CALCS_VERSION_STONEY,
BW_CALCS_VERSION_VEGA10
};
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -86,6 +86,7 @@
#define VI_POLARIS10_P_A0 80
#define VI_POLARIS11_M_A0 90
#define VI_POLARIS12_V_A0 100
+#define VI_VEGAM_A0 110
#define VI_UNKNOWN 0xFF
@@ -98,14 +99,9 @@
(eChipRev < VI_POLARIS11_M_A0))
#define ASIC_REV_IS_POLARIS11_M(eChipRev) ((eChipRev >= VI_POLARIS11_M_A0) && \
(eChipRev < VI_POLARIS12_V_A0))
-#if defined(CONFIG_DRM_AMD_DC_VEGAM)
-#define VI_VEGAM_A0 110
#define ASIC_REV_IS_POLARIS12_V(eChipRev) ((eChipRev >= VI_POLARIS12_V_A0) && \
(eChipRev < VI_VEGAM_A0))
#define ASIC_REV_IS_VEGAM(eChipRev) (eChipRev >= VI_VEGAM_A0)
-#else
-#define ASIC_REV_IS_POLARIS12_V(eChipRev) (eChipRev >= VI_POLARIS12_V_A0)
-#endif
/* DCE11 */
#define CZ_CARRIZO_A0 0x01
--- a/drivers/gpu/drm/amd/display/include/dal_types.h
+++ b/drivers/gpu/drm/amd/display/include/dal_types.h
@@ -40,9 +40,7 @@ enum dce_version {
DCE_VERSION_10_0,
DCE_VERSION_11_0,
DCE_VERSION_11_2,
-#if defined(CONFIG_DRM_AMD_DC_VEGAM)
DCE_VERSION_11_22,
-#endif
DCE_VERSION_12_0,
DCE_VERSION_MAX,
DCN_VERSION_1_0,