From c8737fb9ff8f44c43080b9aee75602ae8862ec1e Mon Sep 17 00:00:00 2001
From: Tom St Denis <tom.stdenis@amd.com>
Date: Fri, 20 Mar 2020 14:21:58 -0400
Subject: drm/amd/amdgpu: Add GFX9.1 PWR_MISC_CNTL_STATUS register to headers
Git-commit: 1f02c97b32dd983ab1646bc77d7e75c52ca97c5a
Patch-mainline: v5.8-rc1
References: jsc#SLE-12680, jsc#SLE-12880, jsc#SLE-12882, jsc#SLE-12883, jsc#SLE-13496, jsc#SLE-15322
The registers are needed for umr and not in the headers. I left them
in the gfx_v9_0.c since it includes 9.0 and 9.4 headers and including
9.1 headers would result in a lot of duplicate registers clashing.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Patrik Jakobsson <pjakobsson@suse.de>
---
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h | 2 ++
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h | 5 +++++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
index 030e0020902b..ad61ffb0fd97 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
@@ -159,6 +159,8 @@
#define mmCP_DE_LAST_INVAL_COUNT_BASE_IDX 0
#define mmCP_DE_DE_COUNT 0x00c4
#define mmCP_DE_DE_COUNT_BASE_IDX 0
+#define mmPWR_MISC_CNTL_STATUS 0x0183
+#define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0
#define mmCP_STALLED_STAT3 0x019c
#define mmCP_STALLED_STAT3_BASE_IDX 0
#define mmCP_STALLED_STAT1 0x019d
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h
index 13bfc2e6e16f..6cc63562fd55 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h
@@ -801,6 +801,11 @@
//CP_DE_DE_COUNT
#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL
+//PWR_MISC_CNTL_STATUS
+#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0
+#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1
+#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L
+#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L
//CP_STALLED_STAT3
#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1
--
2.28.0