From 240a9ec99f37450ec26c9a3d06cf6168771c0dc9 Mon Sep 17 00:00:00 2001
From: Kenneth Feng <kenneth.feng@amd.com>
Date: Thu, 7 May 2020 14:33:06 +0800
Subject: drm/amd/powerplay: show gfxclk=0 in gfxoff state
Git-commit: ba818620db217b5ed1f8fc65fb14d63772f55836
Patch-mainline: v5.9-rc1
References: jsc#SLE-12680, jsc#SLE-12880, jsc#SLE-12882, jsc#SLE-12883, jsc#SLE-13496, jsc#SLE-15322
The instant retrieved gfxclk value should be 0 in gfxoff state.
This can be fetched with gfxoff enabled.
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Patrik Jakobsson <pjakobsson@suse.de>
---
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 10114132fdd8..c924ecf2899f 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -709,9 +709,6 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
uint32_t mark_index = 0;
uint32_t gen_speed, lane_width;
- if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
- amdgpu_gfx_off_ctrl(adev, false);
-
switch (clk_type) {
case SMU_GFXCLK:
case SMU_SCLK:
@@ -727,6 +724,10 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
/* 10KHz -> MHz */
cur_value = cur_value / 100;
+ /* no need to disable gfxoff when retrieving the current gfxclk */
+ if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
+ amdgpu_gfx_off_ctrl(adev, false);
+
ret = smu_get_dpm_level_count(smu, clk_type, &count);
if (ret)
goto print_clk_out;
--
2.29.2