From e0e581c7ee381f48c721ca77e3772f324756d755 Mon Sep 17 00:00:00 2001
From: Tom St Denis <tom.stdenis@amd.com>
Date: Mon, 15 Jun 2020 12:17:46 -0400
Subject: drm/amd/amdgpu: Fix SQ_DEBUG_STS_GLOBAL* registers
Git-commit: e3569fab49886123c81f18d675fb1719d73cf27d
Patch-mainline: v5.9-rc1
References: jsc#SLE-12680, jsc#SLE-12880, jsc#SLE-12882, jsc#SLE-12883, jsc#SLE-13496, jsc#SLE-15322
Forgot to subtract the SOC15 IP offsetand add the BASE_IDX values.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Patrik Jakobsson <pjakobsson@suse.de>
---
.../gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h | 6 ++++--
.../gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h | 6 ++++--
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h | 9 ++++++---
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h | 9 ++++++---
.../gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h | 9 ++++++---
5 files changed, 26 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
index aab3d22c3b0f..baac40fa70e7 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
@@ -21,8 +21,10 @@
#ifndef _gc_10_1_0_OFFSET_HEADER
#define _gc_10_1_0_OFFSET_HEADER
-#define mmSQ_DEBUG_STS_GLOBAL 0x2309
-#define mmSQ_DEBUG_STS_GLOBAL2 0x2310
+#define mmSQ_DEBUG_STS_GLOBAL 0x0309
+#define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
+#define mmSQ_DEBUG_STS_GLOBAL2 0x0310
+#define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
// addressBlock: gc_sdma0_sdma0dec
// base address: 0x4980
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
index 16c7f6f2467e..0bde3b4e9567 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
@@ -22,8 +22,10 @@
#ifndef _gc_10_3_0_OFFSET_HEADER
#define _gc_10_3_0_OFFSET_HEADER
-#define mmSQ_DEBUG_STS_GLOBAL 0x2309
-#define mmSQ_DEBUG_STS_GLOBAL2 0x2310
+#define mmSQ_DEBUG_STS_GLOBAL 0x0309
+#define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
+#define mmSQ_DEBUG_STS_GLOBAL2 0x0310
+#define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
// addressBlock: gc_sdma0_sdma0dec
// base address: 0x4980
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
index e3e1a9c1153b..12d451e5475b 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
@@ -21,9 +21,12 @@
#ifndef _gc_9_0_OFFSET_HEADER
#define _gc_9_0_OFFSET_HEADER
-#define mmSQ_DEBUG_STS_GLOBAL 0x2309
-#define mmSQ_DEBUG_STS_GLOBAL2 0x2310
-#define mmSQ_DEBUG_STS_GLOBAL3 0x2311
+#define mmSQ_DEBUG_STS_GLOBAL 0x0309
+#define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
+#define mmSQ_DEBUG_STS_GLOBAL2 0x0310
+#define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
+#define mmSQ_DEBUG_STS_GLOBAL3 0x0311
+#define mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
// addressBlock: gc_grbmdec
// base address: 0x8000
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
index 6b1ad9082a2c..d17d1e622e4f 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
@@ -21,9 +21,12 @@
#ifndef _gc_9_1_OFFSET_HEADER
#define _gc_9_1_OFFSET_HEADER
-#define mmSQ_DEBUG_STS_GLOBAL 0x2309
-#define mmSQ_DEBUG_STS_GLOBAL2 0x2310
-#define mmSQ_DEBUG_STS_GLOBAL3 0x2311
+#define mmSQ_DEBUG_STS_GLOBAL 0x0309
+#define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
+#define mmSQ_DEBUG_STS_GLOBAL2 0x0310
+#define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
+#define mmSQ_DEBUG_STS_GLOBAL3 0x0311
+#define mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
// addressBlock: gc_grbmdec
// base address: 0x8000
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h
index f377354e850e..c30720277912 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h
@@ -21,9 +21,12 @@
#ifndef _gc_9_2_1_OFFSET_HEADER
#define _gc_9_2_1_OFFSET_HEADER
-#define mmSQ_DEBUG_STS_GLOBAL 0x2309
-#define mmSQ_DEBUG_STS_GLOBAL2 0x2310
-#define mmSQ_DEBUG_STS_GLOBAL3 0x2311
+#define mmSQ_DEBUG_STS_GLOBAL 0x0309
+#define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
+#define mmSQ_DEBUG_STS_GLOBAL2 0x0310
+#define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
+#define mmSQ_DEBUG_STS_GLOBAL3 0x0311
+#define mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
// addressBlock: gc_grbmdec
// base address: 0x8000
--
2.29.2