From 05c7c5c86c0566088dc6351c8bc85391ea95659b Mon Sep 17 00:00:00 2001
From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Date: Tue, 28 Jan 2020 15:15:10 -0500
Subject: drm/amd/display: Wait for DMCUB to finish loading before executing
Git-commit: 20a5e52f37e71e51defb09f8fd6ad5d84bcd6c90
Patch-mainline: v5.7-rc1
References: jsc#SLE-12680, jsc#SLE-12880, jsc#SLE-12882, jsc#SLE-12883, jsc#SLE-13496, jsc#SLE-15322
commands
[Why]
When we execute the first command for ASIC_INIT for command table
offloading we can hit a timing scenario such that the interrupts
for the inbox wptr haven't been enabled yet and the first command
is ignored until the second command is sent.
[How]
This happens when either the SCRATCH0 is already the correct status
code or autoload check is unsupported.
Clear SCRATCH0 during reset.
Also ensure that we don't accidentally reset the ASIC again in case
of a hang by clearing GPINT while we're at it.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Chris Park <Chris.Park@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Patrik Jakobsson <pjakobsson@suse.de>
---
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
index 993e47e99fbe..63bb9e2c81de 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
@@ -116,6 +116,10 @@ void dmub_dcn20_reset(struct dmub_srv *dmub)
break;
}
+ /* Clear the GPINT command manually so we don't reset again. */
+ cmd.all = 0;
+ dmub->hw_funcs.set_gpint(dmub, cmd);
+
/* Force reset in case we timed out, DMCUB is likely hung. */
}
@@ -124,6 +128,7 @@ void dmub_dcn20_reset(struct dmub_srv *dmub)
REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);
REG_WRITE(DMCUB_INBOX1_RPTR, 0);
REG_WRITE(DMCUB_INBOX1_WPTR, 0);
+ REG_WRITE(DMCUB_SCRATCH0, 0);
}
void dmub_dcn20_reset_release(struct dmub_srv *dmub)
--
2.28.0