From 1b155da622819f94b8f0b9b72de2daa228c3be69 Mon Sep 17 00:00:00 2001
From: Matt Roper <matthew.d.roper@intel.com>
Date: Tue, 3 Mar 2020 11:50:43 -0800
Subject: drm/i915/ehl: Check PHY type before reading DPLL frequency
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Git-commit: 56ed441aa1eda6acbbe5a97178915ca93cf9c0ee
Patch-mainline: v5.7-rc1
References: jsc#SLE-12680, jsc#SLE-12880, jsc#SLE-12882, jsc#SLE-12883, jsc#SLE-13496, jsc#SLE-15322
intel_ddi_clock_get() tests the DPLL ID against DPLL_ID_ICL_TBTPLL (2)
to determine whether to try to descend into a TBT-specific handler.
However this test will also be true when DPLL4 on EHL is used since that
shares the same DPLL ID (2).
Add an extra check to ensure the PHY is actually a Type-C PHY before
descending into the TBT handling. This should ensure EHL still takes
the correct code path and somewhat future-proof the code as well.
v2: Drop the gen+ check since only gen11+ platforms can have Type-C
outputs. (Imre)
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Closes: https://gitlab.freedesktop.org/drm/intel/issues/1369
Fixes: 45e4728b87ad ("drm/i915: Move DPLL frequency calculation to intel_dpll_mgr.c")
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200303195043.959913-1-matthew.d.roper@intel.com
Signed-off-by: Patrik Jakobsson <pjakobsson@suse.de>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 284219da7df8..73c9d4fda6f8 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1376,8 +1376,9 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
- if (INTEL_GEN(dev_priv) >= 11 &&
+ if (intel_phy_is_tc(dev_priv, phy) &&
intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll) ==
DPLL_ID_ICL_TBTPLL)
pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv,
--
2.28.0