From c6447868b5fc6f61aa7d070ecb8fbb2344b198d8 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Sat, 20 Jun 2020 15:46:52 +1000
Subject: drm/nouveau/kms/nv50-: use NVIDIA's headers for wndw blend_set()
Git-commit: fbc318bdbb43a151b4f60ff3b86d577daeb63791
Patch-mainline: v5.9-rc1
References: jsc#SLE-12680, jsc#SLE-12880, jsc#SLE-12882, jsc#SLE-12883, jsc#SLE-13496, jsc#SLE-15322

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Patrik Jakobsson <pjakobsson@suse.de>
---
 drivers/gpu/drm/nouveau/dispnv50/wndw.c     | 12 +++---
 drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 43 ++++++++++++++++-----
 2 files changed, 39 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c
index 8f6717267df1..447ecc9fec42 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c
@@ -334,17 +334,17 @@ nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw, bool modeset,
 		asyw->blend.k1 = asyw->state.alpha >> 8;
 		switch (asyw->state.pixel_blend_mode) {
 		case DRM_MODE_BLEND_PREMULTI:
-			asyw->blend.src_color = 2; /* K1 */
-			asyw->blend.dst_color = 7; /* NEG_K1_TIMES_SRC */
+			asyw->blend.src_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1;
+			asyw->blend.dst_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC;
 			break;
 		case DRM_MODE_BLEND_COVERAGE:
-			asyw->blend.src_color = 5; /* K1_TIMES_SRC */
-			asyw->blend.dst_color = 7; /* NEG_K1_TIMES_SRC */
+			asyw->blend.src_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_SRC;
+			asyw->blend.dst_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC;
 			break;
 		case DRM_MODE_BLEND_PIXEL_NONE:
 		default:
-			asyw->blend.src_color = 2; /* K1 */
-			asyw->blend.dst_color = 4; /* NEG_K1 */
+			asyw->blend.src_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1;
+			asyw->blend.dst_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1;
 			break;
 		}
 		if (memcmp(&armw->blend, &asyw->blend, sizeof(asyw->blend)))
diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
index b071cca8dfbf..8dd1e89f4725 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
@@ -105,16 +105,39 @@ wndwc37e_blend_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
 	if ((ret = PUSH_WAIT(push, 8)))
 		return ret;
 
-	PUSH_NVSQ(push, NVC37E, 0x02ec, asyw->blend.depth << 4,
-				0x02f0, asyw->blend.k1,
-				0x02f4, asyw->blend.dst_color << 12 |
-					asyw->blend.dst_color << 8 |
-					asyw->blend.src_color << 4 |
-					asyw->blend.src_color,
-				0x02f8, 0xffff0000,
-				0x02fc, 0xffff0000,
-				0x0300, 0xffff0000,
-				0x0304, 0xffff0000);
+	PUSH_MTHD(push, NVC37E, SET_COMPOSITION_CONTROL,
+		  NVDEF(NVC37E, SET_COMPOSITION_CONTROL, COLOR_KEY_SELECT, DISABLE) |
+		  NVVAL(NVC37E, SET_COMPOSITION_CONTROL, DEPTH, asyw->blend.depth),
+
+				SET_COMPOSITION_CONSTANT_ALPHA,
+		  NVVAL(NVC37E, SET_COMPOSITION_CONSTANT_ALPHA, K1, asyw->blend.k1) |
+		  NVVAL(NVC37E, SET_COMPOSITION_CONSTANT_ALPHA, K2, 0),
+
+				SET_COMPOSITION_FACTOR_SELECT,
+		  NVVAL(NVC37E, SET_COMPOSITION_FACTOR_SELECT, SRC_COLOR_FACTOR_MATCH_SELECT,
+							       asyw->blend.src_color) |
+		  NVVAL(NVC37E, SET_COMPOSITION_FACTOR_SELECT, SRC_COLOR_FACTOR_NO_MATCH_SELECT,
+							       asyw->blend.src_color) |
+		  NVVAL(NVC37E, SET_COMPOSITION_FACTOR_SELECT, DST_COLOR_FACTOR_MATCH_SELECT,
+							       asyw->blend.dst_color) |
+		  NVVAL(NVC37E, SET_COMPOSITION_FACTOR_SELECT, DST_COLOR_FACTOR_NO_MATCH_SELECT,
+							       asyw->blend.dst_color),
+
+				SET_KEY_ALPHA,
+		  NVVAL(NVC37E, SET_KEY_ALPHA, MIN, 0x0000) |
+		  NVVAL(NVC37E, SET_KEY_ALPHA, MAX, 0xffff),
+
+				SET_KEY_RED_CR,
+		  NVVAL(NVC37E, SET_KEY_RED_CR, MIN, 0x0000) |
+		  NVVAL(NVC37E, SET_KEY_RED_CR, MAX, 0xffff),
+
+				SET_KEY_GREEN_Y,
+		  NVVAL(NVC37E, SET_KEY_GREEN_Y, MIN, 0x0000) |
+		  NVVAL(NVC37E, SET_KEY_GREEN_Y, MAX, 0xffff),
+
+				SET_KEY_BLUE_CB,
+		  NVVAL(NVC37E, SET_KEY_BLUE_CB, MIN, 0x0000) |
+		  NVVAL(NVC37E, SET_KEY_BLUE_CB, MAX, 0xffff));
 	return 0;
 }
 
-- 
2.29.2