From f9d9189d9c96629a67ba935af3f5112dfd3a285d Mon Sep 17 00:00:00 2001
From: Shubhashree Dhar <dhar@codeaurora.org>
Date: Wed, 27 Nov 2019 15:46:07 +0530
Subject: msm:disp:dpu1: Fix core clk rate in display driver
Git-commit: fea2d7d98e02adacde5a37ef1cfdacec5645b88d
Patch-mainline: v5.6-rc1
References: jsc#SLE-12680, jsc#SLE-12880, jsc#SLE-12882, jsc#SLE-12883, jsc#SLE-13496, jsc#SLE-15322
Fix max core clk rate during dt parsing in display driver.
Signed-off-by: Shubhashree Dhar <dhar@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Patrik Jakobsson <pjakobsson@suse.de>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c
index ec1437b0ef75..078afc5f5882 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c
@@ -175,6 +175,7 @@ int msm_dss_parse_clock(struct platform_device *pdev,
continue;
mp->clk_config[i].rate = rate;
mp->clk_config[i].type = DSS_CLK_PCLK;
+ mp->clk_config[i].max_rate = rate;
}
mp->num_clk = num_clk;
--
2.28.0