From 0ec083e50ca816953e65e3209c7199cd1a203ddc Mon Sep 17 00:00:00 2001
From: Dave Jiang <dave.jiang@intel.com>
Date: Wed, 29 Jul 2020 08:57:26 -0700
Subject: [PATCH] dmaengine: idxd: clear misc interrupt cause after read
Git-commit: 0ec083e50ca816953e65e3209c7199cd1a203ddc
Patch-mainline: v5.10-rc1
References: jsc#SLE-12688
Move the clearing of misc interrupt cause to immediately after reading the
register in order to allow the next interrupt to be asserted.
Suggested-by: Nikhil Rao <nikhil.rao@intel.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/159603824665.28647.5344356370364397996.stgit@djiang5-desk3.ch.intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Acked-by: Takashi Iwai <tiwai@suse.de>
---
drivers/dma/idxd/irq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/idxd/irq.c b/drivers/dma/idxd/irq.c
index b5142556cc4e..11ac0703b371 100644
--- a/drivers/dma/idxd/irq.c
+++ b/drivers/dma/idxd/irq.c
@@ -76,6 +76,7 @@ irqreturn_t idxd_misc_thread(int vec, void *data)
bool err = false;
cause = ioread32(idxd->reg_base + IDXD_INTCAUSE_OFFSET);
+ iowrite32(cause, idxd->reg_base + IDXD_INTCAUSE_OFFSET);
if (cause & IDXD_INTC_ERR) {
spin_lock_bh(&idxd->dev_lock);
@@ -133,7 +134,6 @@ irqreturn_t idxd_misc_thread(int vec, void *data)
dev_warn_once(dev, "Unexpected interrupt cause bits set: %#x\n",
val);
- iowrite32(cause, idxd->reg_base + IDXD_INTCAUSE_OFFSET);
if (!err)
goto out;
--
2.26.2